The Evolution of the Extension Implant Part IV

Perhaps the most innovative and effective Extension implant does not involve an implant at all, but is instead an etch followed by a selective epitaxial deposition.

In this Extension fabrication methodology the Source/Drains regions in a planar device are etched away in the normal fashion to accommodate the replacement Source/Drain stressor material (SiGe for the PMOS device and SiC for the NMOS device). This etch is sometimes called the “Sigma” etch. It begins with an HF etch to remove any native oxide present on the surface of the silicon. (Note that the Halo implant is already in place.)

Next, the Source/Drain regions are etched out using a wet etch of NH[SUB]4[/SUB]OH. Alternate etch chemistries that will also work for this task are NH[SUB]3[/SUB]OH, TMAH, KOH, NaOH, BTMH or amine-based etchants.

Initially, the wet etch creates a facet in the lateral direction for a short distance in the channel region beneath the spacer and the gate dielectric and along the {010} plane (refer to Figure #1). This is followed by the formation in the Source/Drain region of an angled facet along the {111} plane. This etch chemistry is substantially preferential in the {111} crystallographic plane and therefore the silicon is etched more deeply in that direction.

The hard mask on the top of the Gate Electrode protects the polysilicon during this wet etch.

The {010} facet creates a precisely shaped Extension cavity that will define the Extension region of the transistor, and when it is filled with N-doped silicon, it will become the Extension of the transistor.

The Source/Drain cavities are then filled with Epitaxially deposited SiC or simply conventional Silicon that is in-situ doped with Phosphorus (refer to Figure #2).

In this methodology the Extension of the transistor is defined by the precisely etched {010} undercut of the gate dielectric, as illustrated. It is claimed that this well-defined structure provides superior dimensional control compared to an implanted Extension, as well as improved short channel effects.

Figure #3 displays the resulting structure when this technique is employed with two adjacent Gates Electrodes. In this instance the wet etch is self-limiting.

After forming the {010} facet, the wet etch will progress along the two {111} facets of the two adjacent transistors until the two {111} facets meet and form a “V” shape. Because of the etch’s directional preference for the {111} plane, once the facets from the two transistors join up to form a “V”, the rate at which the etch proceeds into the substrate decreases. In this respect the etch is self-limiting.

In addition, the depth of the joined facets formed by the “V” can be controlled by controlling the pitch of the adjacent transistors.

The Source/Drain cavities are then filled with N-doped SiC or with Epitaxially deposited Silicon that is in-situ doped with Phosphorus (refer to figure #4).

The Extension of each transistor is now defined by the precisely etched {010} undercut of the gate dielectric, as illustrated. Thus, the Extension of the transistor is formed without an implant operation and this reduces process complexity and produces a superior Extension structure. It is also claimed that this well-defined Extension provides superior dimensional control than an implanted Extension as well as improved short channel effects.

This content was authored by Jerry Healey of Threshold Systems Inc. For detailed information on the entire process flows for the 10/7/5nm nodes attend the course “Advanced CMOS Technology 2019” to be held on May 22, 23, 24 in Milpitas California.

Also read: The Evolution of the Extension Implant Part III