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Cadence Releases Enterprise-Level FPGA Prototyping

Cadence Releases Enterprise-Level FPGA Prototyping
by Bernard Murphy on 06-04-2019 at 5:00 am

Big prototyping hardware is essential to modern firmware and software development for pre-silicon, multi-billion gate hardware. For hardware verification it complements emulation, running fast enough for realistic testing on big software loads while still allowing fast-switch to emulation for more detailed debug where needed. For software and firmware, whose development cost can often far exceed that for hardware, it’s vital to be able to comprehensively regress existing stacks and tune for the new hardware. Finally, validating the full system demands running the hardware plus software stack embedded in some manifestation of that system a reasonable speed. FPGA prototyping provides the best balance of performance, software debug and necessary hardware debug for this level of verification.

It takes a lot of big FPGAs to map these huge designs, meaning you really want this to be a data center-class capability, especially since you will want to leverage this investment as effectively as possible, supporting efficient loading of a range of design sizes and workloads and round-the-clock operation. Which is why Cadence just announced Protium X1 to support enterprise prototyping, scalable up to multi-billion gate designs. These systems have a unified front-end with Protium S1 (which you can continue to use as the desktop equivalent for smaller tasks), and both continue to have a unified front-end with the Palladium emulators.

Juergen Jaeger (PM director at Cadence) told me that the X1 is a blade-based system, 8 blades to a rack; you can use the Cadence X1 rack or your own rack. Each blade is completely self-sufficient, has low power consumption with no special cooling requirements, and is compatible with standard data center cooling expectations. They’re also designed for data center management, allowing for remote power supply monitoring and control for example.

For multi-user usage, users can partition down to a single FPGA (with up to 48 users per rack) as appropriate, delivering 20M ASIC gates running up to 50MHz. Or you can take over multiple racks (1B gates per rack) running at around 5MHz. Speeds here are for automated partitioning; with manual optimization I was told you can double performance.

Frank Schirrmeister (needs no introduction) stresses that X1 extends the range of the S1 prototyper. You can and should continue to use your S1 desktop systems as you have been using them. X1 extends the reach of prototyping by 64X on the same underlying S1 architecture. Cadence supports all of this with a brand-new Pathfinder partitioner and strategies designed to optimize pin-multiplexing through SERDES, LVDS, etc. for FPGA-to-FPGA connectivity. Manual optimization includes the usual partitioning and inter-FPGA logic options, also ability to substitute native interfaces such as PCIe for design IPs. Blade and rack partitioning through cabling are supported by a GUI to configure and check setup.

Very importantly, Cadence have put a lot of work into accelerating bring-up (for X1 and S1 since these have a common front-end). Analysis on multiple customer designs shows Protium bringup 80-90% faster than comparable systems,. This reduced in one example a bringup time of 20 weeks down to 2 weeks, making early stage firmware/software regression and debug much more practical. For system/in-circuit validation, these systems continue to support Cadence’s rich portfolio of SpeedBridges, which has to be a real plus in hardware-in-loop (HIL) testing requirements found in automotive testing, as one example.

For hardware debug you can use Indago, Verdi or similarly-capable debuggers. As you shift to firmware/software debug you’re more likely to be using Lauterbach, the ARM Keil debugger or other tools of that nature. Juergen told me that they know a variety of debug tools will be needed so they put a lot of debug investment into data capture and creation, also control of the debug system for backdoor memory access, starting and stopping the clock, all the features that have to be efficiently supported by the prototyping hardware, whatever debugger you use at any given stage.

More and more verification capability is moving to datacenters and to the cloud, following trends in software in general, making for better utilization of in-house capital investments and much easier scalability to handle peaks in the cloud, or longer term to rebalance in-house investment strategies. Protium X1 looks like a very logical step along that path. You will be able to learn more about the X1 at DAC, also you can check out the features and specs HERE.