Webinar: Verisium Debug for UVM Testbench

Date: Wednesday, October 4, 2023

Time: 11:00am PT | 1:00pm CT | 2:00pm ET

Verisium Debug offers comprehensive debugging capabilities. From RTL and UVM testbench to UPF low-power designs, Cadence’s unified debugging platform helps users debug. In this webinar, users will learn about the available features in Verisium Debug for UVM testbench and use these unique capabilities to visualize and debug the UVM testbench.

What you will learn

• Understand the features available in Verisium Debug
• ​Learn about the UVM debug capabilities in Verisium Debug
• Learn to debug UVM testbench using Verisium Debug

Who should attend

• Design engineers
• Verification engineers
• CAD engineers

REGISTER HERE