Webinar: Stratus HLS Automated Power Shutoff to Minimize Power and Retention Registers

Date: Wednesday, September 27, 2023

Time: 12:00pm PDT | 3:00pm EDT

Power Shutoff is a popular technique for saving power during functionally idle periods. Implementing Power Shutoff requires a detailed understanding of which resisters must be retained to enable bring-up from the power-off state. Identifying the minimal set of retention registers is challenging and grows more difficult with design complexity.

This CadenceTECHTALK introduces a novel High-Level Synthesis-based solution for the automated implementation of Power Shutoff. This solution automatically identifies and implements Power Shutoff using the minimal set of retention registers, yielding the lowest leakage power and saving weeks of implementation time vs. manual methods.

Join this webinar to learn how to apply this technology to your own design and interact with product experts who will demonstrate the technology in a real-world testcase. Design engineers working on low-power digital IC designs or algorithms will benefit from this TECHTALK.

REGISTER HERE