Webinar: PCIe 6.0 Simulation and Electrical Testing for High Data-Bandwidth Applications

*Work email is required. We need to know who we are presenting to*

PCI Express® (PCIe®) technology has been the standard interconnect inside computers providing high bandwidth and low latency to meet customer demand, continuously evolving , keeping pace, and driving future innovation with PCIe 6.0. To ensure seamless operation & robust system interoperability, complex process like iterative simulation and silicon electrical validation process are required.

In this Synopsys and Tektronix webinar, we will delve into system simulation to verify that the SerDes can properly establish and maintain communication links with other devices through link training and retraining processes with reasonable signal integrity, new voltage and timing analysis techniques, as well as ongoing PCIe compliance testing development to ensure that the SerDes & overall PCIe system meets the standard specifications defined by PCIe standards using specialized test equipment to assess the signal quality to ensure the proper bit error rate is achieved.

SPEAKERS

David Bouse is a Principal Technology Leader at Tektronix and an active contributor to PCI-SIG with expertise in highspeed SERDES including transmitter and receiver test methodologies, DSP algorithms for NRZ/PAM4 signaling, clock characterization, and automation software architecture.

Madhumita Sanyal is a Sr. Staff Technical Manager for Synopsys high-speed SerDes portfolio. She has +17 years of experience in design and application of ASIC WLAN products, logic libraries, embedded memories, and mixed-signal IP.

*This webinar is in partnership with SemiWiki and Synopsys*

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