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Wafer-Level Packaging Symposium

February 13, 2024 - February 15, 2024

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Formatting Advanced Packaging for the AI Era

The development of Advanced Package Technology is undergoing a massive change because Electrical System Architects are directly driving package performance requirements, something which has never happened before. Previously System Architects designed circuits around package limitations because pushing package technologies outside of their “comfort zones” often led to undesirable results.

With the rise in transistor costs and the need to improve power efficiency, Silicon Architects have little choice but to push advanced package technologies well beyond their comfort zones.

The Wafer-Level Packaging Symposium will bring together the semiconductor industry’s most respected authorities to address all aspects of wafer-level, 3D device packaging, advanced manufacturing & test technologies. Addressing wafer-level packaging, 3D, and Advanced Manufacturing & Test technologies, the Wafer-Level Packaging Symposium will be at the forefront of packaging technology evolution. The conference will feature attendees from around the globe in the heart of Silicon Valley to immerse themselves in the latest technology and business trends.

Be a Key Contributor

Submit an abstract for the 2024 technical program. Abstracts are due October 31, 2023.

Submit an Abstract

 Unlock New Horizons in Semiconductor Packaging! 

Join our Professional Development Courses on February 15, 2024! Are you ready to take your career in semiconductor packaging to the next level? Look no further! We’re thrilled to present two exceptional professional development courses on Thursday, February 15, 2024, designed to empower you with cutting-edge knowledge and insights.

View Course Information

A conference session room at WLPS


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February 13, 2024
February 15, 2024
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Hyatt Regency San Francisco Airport
1333 Bayshore Highway
Burlingame, CA 94010 United States
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