M-PCIe, Data Converters, and USB 3.0 SSIC at IP SoC 2013

Synopsys is taking IP-SOC 2013 seriously, as the company will hold several presentations, starting with a Keynote: “Virtual Prototyping – A Reality Check”, by Johannes Stahl, Director, Product Marketing, System-Level Solutions, Synopsys, highlighting current industry practice around putting virtual prototyping to work for early software development, with specific emphasis on the value chain for the creation and use of virtual prototypes. Virtual prototyping allows for concurrent engineering, or developing hardware and software in parallel. Concurrent engineering has clearly a strong impact on Time-To-Market (TTM), and TTM has a direct impact on the balance sheet for chip makers.

On my side, I am pretty excited about two IP related presentations:

Low-Power Analysis and Verification of USB Super Speed Inter-Chip (SSIC) IP: The presentation highlights a low-power analysis that showcases the power savings achieved in SSIC IP with and without use of the hibernation state.

Moving PCI Express to Mobile (M‑PCIe): This presentation will begin with an overview of the M‑PCIe specification and its application space, and then go into details such as bandwidth and clocking considerations, PHY interface differences, power management impacts, and the tradeoffs related to choices around link-layer changes.
This presentation will be made by Richard Solomon, Technical Marketing Manager, PCI Express Controller IP at Synopsys. When you notice that Richard is one of the Directors of PCI-SIG Board for (many) years, if you want to better understand about PCI Express and M-PCIe, you should not miss this presentation.

If you go to Synopsys booth (#12), you will see a live demonstration of M-PCIe solution:
DesignWare IP for M‑PCIe Interoperability Demonstration
This demonstration showcases the DesignWare IP for M‑PCIe and the DesignWare MIPI HS-Gear3 M-PHY interoperating with a leading semiconductor company’s M‑PCIe solution. View a preview of the demonstration.

The latest paper, discussing Analog IP architecture, will be presented by Manuel Mota:
Scalable Architectures for Analog IP on Advanced Process Nodes: This presentation compares the attributes of common ADC architectures, including the SAR-based architecture, for use in medium and high-speed 28-nm ADCs.

To summarize, Synopsys will present about Mobile Express (MIPI and PCIe), SuperSpeed chip to chip solution (SSUSB), ADC architectures targeting 28nm technology node and Virtual Prototyping, a TTM accelerator…All of these IP or EDA tool being used to develop advanced SoC for Mobile applications, certainly the fastest growing, and probably the largest market segment nowadays.

Presenters:

Johannes Stahl, Director, Product Marketing, System-Level Solutions, Synopsys
Dr. Johannes Stahl is responsible for all software development, architecture design and algorithm design tools at Synopsys. Before Synopsys he had marketing responsibility in the executive team at CoWare, where he was managing major product lines as well as all IP partner relationships. During his earlier tenure at Synopsys, Dr. Stahl was responsible for their SystemC products as well as driving the rollout of the SystemC initiative. He has lead a Synopsys wireless engineering services team, that delivered custom IP cores for wireless and broadcasting applications to major semiconductor companies. He holds Dipl.-Ing. and Dr.-Ing. Degrees in Electrical Engineering from Aachen Technical University, Germany.

Manuel Mota, Technical Marketing manager, Analog IP, Synopsys
Marketing Manager with twelve plus years of experience in the semiconductor industry, covering several design and Managerial roles from Engineering Teams to Product and Marketing.
Special focus in Broadband Communications and Multimedia systems, with broad expertise is Analog and Mixed Signal IP product definition and marketing. Extensive experience with International customer negotiation.
Background in Analog/Mixed Signal design, from single function blocks (PLL, Data Converters) to complete Analog Front Ends and Mixed Signal ASICs.

Richard Solomon,Technical Marketing Manager, PCI Express Controller IP, Synopsys

If you plan to attend to IP-SOC, on November 6, 7 in Grenoble (France), just contact me at eric.esteve@ip-nest.com we could meet during the conference.

Eric Esteve from IPNEST

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