Formal verification has always appeared daunting to me and I suspect to many other people also. Logic simulation feels like a “roll your sleeves up and get the job done” kind of verification, easily understood, accessible to everyone, little specialized training required. Formal methods for many years remained the domain of academics and one-time-academics performing an essentially black-box service to solve really hard problems unreachable in simulation. That’s changed, because those hard problems are becoming much more common and because verification tool providers have made it much easier to attack many cases without needing a PhD or induction into the formal priesthood. Better yet, there are excellent books to introduce novices to the domain and walk them through their first steps in using those tools.
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One thing we felt was missing was a higher-level introduction, for a verification engineer, manager or director who is curious about formal but not yet ready to commit. They don’t want a tutorial; they want to know first “is this right for my organization?” “Is it really going to improve our verification quality or throughput?” “What are we going to have to do differently?” We wrote “Finding Your Way Through Formal Verification” for them. “We” here is myself (Bernard Murphy), Manish Pandey and Sean Safarpour. The book was published by SemiWiki and is available for download in the handouts section of this webinar.
Bernard Murphy – SemiWiki
Bernard Murphy is a freelance blogger and author, content marketing/messaging advisor for several companies and serves on the board of Mother Lode Wildlife Care in the California Gold Country. In a previous life he held down a real job as CTO at Atrenta. Earlier still, he held technical contributor, management, sales and marketing roles variously at Cadence, National Semiconductor, Fairchild and Harris Semiconductor. In his re-invention as a writer, Bernard has published well over 400 blogs between SemiWiki and EETimes. He received his BA in Physics and D. Phil in Nuclear Physics from the University of Oxford.
Manish Pandey – Synopsys
Manish Pandey is a Fellow at Synopsys, and an Adjunct Professor at Carnegie Mellon University. He completed his PhD in Computer Science from Carnegie Mellon University and a B. Tech. in Computer Science from the Indian Institute of Technology Kharagpur. He currently leads the R&D teams for formal and static technologies, and machine learning at Synopsys. He previously led the development of several static and formal verification technologies at Verplex and Cadence which are in widespread use in the industry. Manish has been the recipient of the IEEE Transaction in CAD Outstanding Young author award and holds over two dozen patents and refereed publications.
Sean Safarpour – Synopsys
Sean Safarpour is the Director of Application Engineering at Synopsys, where his team of specialists support the development and deployment of products such as VC Formal, Hector and Assertion IPs. He works closely with customers and R&D to solve their current verification challenges as well as to define and realize the next generation of formal applications. Prior to Synopsys, Sean was Director of R&D at Atrenta focused on new technology, and VP of Engineering and CTO at Vennsa Technologies, a start-up focused on automated root-cause analysis using formal techniques. Sean received his PhD from the University of Toronto where he completed his thesis entitled “Formal Methods in Automated Design Debugging”.