Successful 3DIC design requires an integrated approach

While the leap from traditional SoC/IC designs to Three-Dimensional Integrated Circuits (3DICs) designs brings new benefits and opportunities, it also introduces new challenges. The benefits include performance, power efficiency, footprint reduction and cost savings. The challenges span design, verification, thermal management, mechanical stress, electrical compliance of the entire 3DIC assembly and reliability. An earlier post on SemiWiki discussed the challenges relating to semiconductor reliability and solutions to address those challenges.

Siemens EDA has recently published a whitepaper that covers the challenges and emerging solutions relating to design, integration, verification, thermal, mechanical and electrical aspects of 3DICs.

The Challenges

Chiplets introduce complexities in the integration process, particularly when utilizing silicon interposers for vertical chiplet stacking. This approach poses hurdles for automated routing tools which are designed with the traditional two-dimensional (2D) perspective in mind. Overlapping geometries on the same layer in different chiplets cannot be treated as a single shape in 3DIC design. Layer mapping, a crucial aspect of the process design kit (PDK), becomes tricky when incorporating chiplets with diverse process technologies into a single 3DIC design. This creates challenges for foundries and outsourced assembly and test (OSAT) companies in understanding the specific layers and associated rules for each chiplet.

The vertical and horizontal stacking of chiplets in 3DICs can lead to increased heat generation. Heat dissipation strategies must be carefully considered to ensure that the heat generated by the components is efficiently distributed and dissipated to prevent hotspots and thermal stress. Additionally, as 3DICs comprise various heterogeneous chiplets, each with its own thermal characteristics, designing a thermal management solution that accommodates these variations becomes complex. Ensuring that the entire 3DIC assembly remains within safe temperature limits while maintaining optimal performance is a significant challenge that designers must address.

Issues related to mechanical stress from components such as ball-grid arrays (BGAs), through-silicon vias (TSVs), and stacked dies need to be captured at the 3DIC assembly level. All of these can negatively impact the electrical behavior of active devices and metal interconnects. Designers must address these challenges by ensuring mechanical stability and minimizing stress-induced performance issues. The combination of thermal and mechanical stress analyses is essential for producing accurate results and enabling effective circuit simulation.

The integration of chiplets with different process technologies and functions necessitates a meticulous consideration of electrical compatibility. Achieving full electrical compliance at both the chip-specific level and down to the device level is essential to ensure proper functionality and reliability. Moreover, the unique vertical stacking of components can introduce challenges related to electrical interference and signal integrity, demanding the implementation of effective shielding and routing strategies. Additionally, as 3DICs involve a complex interplay of diverse chiplets, each with distinct electrical characteristics, it is crucial to manage cross-chiplet coupling and parasitic extraction for protection against electrostatic discharge and latch-up issues.

In essence, early thermal and mechanical stress analysis as well as EM/IR and signal integrity analysis need to be performed. Ensuring that the entire 3DIC assembly operates within specified electrical parameters while avoiding interference and maintaining reliable performance is a central challenge in the electrical domain of 3DIC design.

Solutions from Siemens EDA

All of the above challenges underscore the need for innovative solutions and specialized tools to effectively manage the complexities and ensure successful implementation. Siemens EDA is meeting the challenges of true 3DIC design with solutions such as its Calibre® 3DSTACK tool, Xpedition™ Substrate Integrator (xSI), mPower™ tootsuite, SimCenter™ Flotherm™, Calibre nmLVS™ Query Server technology.

The 3DSTACK tool addresses design rule checking (DRC) and layout vs. schematic (LVS) verification in the context of heterogeneous 3DIC assemblies. It starts by capturing design-specific information, including layer mapping and chiplet placement. This data can be entered manually or automated through Siemens’ Xpedition™ Substrate Integrator (xSI) tool. xSI enables designers to plan and prototype integration approaches. The Calibre 3DSTACK tool automates horizontal and vertical design integration, ensuring layer uniqueness and addressing connectivity challenges. Furthermore, it offers support for cross-die DRC checks and parasitic extraction.

With the mPower toolsuite, designers can assess the 3DIC power domain across all components. The SimCenter Flotherm helps generate accurate chiplet-level thermal models for static and dynamic extraction of the full 3DIC assembly. The 3DIC assembly-level temperature details can be applied back to the chiplet, sub-chip IP or even transistor levels.

All in all, the level of automation and integration enable iterative analysis, reducing the risk of performance and reliability issues in the final design.

Summary

3DICs offer improved performance and power efficiency but also introduce various challenges discussed above. Siemens EDA provides a comprehensive solution that bridges planning, layout automation, 3D physical verification, power analysis, thermal analysis, mechanical analysis, and EM/IR analysis. This solution enables early issue identification and thorough verification of both physical and electrical aspects, ensuring 3DICs deliver all the promised benefits.

You can download Siemens EDA’s entire whitepaper here.

Also Read:

Make Your RISC-V Product a Fruitful Endeavor

Ensuring 3D IC Semiconductor Reliability: Challenges and Solutions for Successful Integration

The Path to Chiplet Architecture