WP_Term Object
    [term_id] => 47
    [name] => Magillem
    [slug] => magillem
    [term_group] => 0
    [term_taxonomy_id] => 47
    [taxonomy] => category
    [description] => 
    [parent] => 157
    [count] => 13
    [filter] => raw
    [cat_ID] => 47
    [category_count] => 13
    [category_description] => 
    [cat_name] => Magillem
    [category_nicename] => magillem
    [category_parent] => 157
    [is_post] => 1

SoC Integration using IP Lifecycle Management Methodology

SoC Integration using IP Lifecycle Management Methodology
by Daniel Payne on 01-27-2017 at 12:00 pm

Small EDA companies often focus on a single point tool and then gradually over time they add new, complementary tools to start creating more of a sub-flow to help you get that next SoC project out on time. The most astute EDA companies often choose to partner with other like-minded companies to create tools that work together well, so that your CAD department doesn’t have to cobble together a working solution. I was pleased to find two such EDA companies that have worked well together on SoC integration using IP lifecycle management methodology, Methodics and Magillem.

There are four tenets to this particular EDA tool interface:


  • Bring IP management to all lifecycle stakeholders through an integrated platform
  • Optimize IP governance
  • Connecting IP design reuse and the IP governance process
  • Manage defects and traceability so that IP modifications are propagated and IP quality improves

    From the Methodics side they offer IP lifecycle management so that SoC design companies have control over both the design and integration of internal and external design elements: libraries, Analog, digital, stand-alone IP. You get traceability and easier reuse by coupling the IP creators with every IP consumer. Collaboration between designers is enabled by use of a centralized catalog, automated notifications, flexible permissions and integrated analytics.

    Related blog – CEO Interview, Simon Butler of Methodics

    Over on the Magillem side you find tools that are IP-Xact based which is derived from IP-reuse methodology to help solve the challenge of maintaining consistency between different representations of your system, by using a single source of data for your specification, hardware design, embedded software and even documentation.

    The Methodics tool is called ProjectIC (yellow), and here’s how it works with Magillem (red) at a conceptual level:

    Now that we’ve seen the big picture, let’s delve one layer lower and start to look at how these two tools create a workflow:

    Related blog – IC Design Management, Build or Buy?

    This workflow will benefit designers in several ways:

    • IP standardization through IP-XACT
    • Fast IP configuration
    • Intelligent IP integration
    • IP design rule checking
    • Hierarchical IP version & bug tracking
    • IP cataloging
    • Automated Magillem reassembly when a workspace is updated
    • Results annotated back to the IP version
    • Notifications automatically sent based on subscription model
    • Takes advantage of the ProjectIC triggers /workflow engine
    • Plugs a major hole in the RTL assembly methodology

    Engineers are always curious about how integrations work under the hood, so the engines from ProjectIC and Magillem communicate with each other transparent to the end-user, so that each workspace load and update action triggers an executable script that runs Magillem in the user’s workspace:

    Related blog – 5 Reasons Why Platform Based Design Can Help Your Next SoC

    Stepping up a level, here’s what a tool user sees when running the ProjectIC tool:

    So this integration is up and running, ready to help out today. The next version of the integration has three refinements:

    • IP-XACT attributes auto-populated on IPs in ProjectIC
    • Changing configurations will automatically trigger IP-XACT attribute refresh
    • Results of multiple workflows will be visible in a single pane

    They say that necessity is the mother of all invention, so it’s refreshing to see that two EDA vendors have taken the time to define, build and test an integration between their tools that will directly help out SoC projects in their quest to be bug-free, and work the first time.