Adding NAND Flash Can Be Tricky

As consumers, we take NAND flash memory for granted. It has worked its way into a vast array of products. These include USB drives, SD cards, wearables, IoT devices, tablets, phones and increasingly SSD’s for computer systems. From the outside the magic of flash memory seems quite simple, but we have to remember that this is a technology that relies on quantum tunneling.

For long term data storage, the spinning hard disk has been difficult to beat. I must confess I remember when bubble memory was going to topple flying head hard drives. But that never happened, but now decades later we are seeing a wholesale shift to flash. If you look at Apple’s computer line up, most have flash drives – either hybrid or pure SSD. Their operating speeds are high enough that they can take advantage of PCIe instead of SATA for their interface in some cases.

Now, what are the potential drawbacks of NAND storage devices? The method for writing to flash memory requires passing an electric charge to a floating gate that is situated between the MOS FET gate and the channel. There are two mechanisms for creating this floating charge, quantum tunneling and hot carrier injection. They both involve relatively high voltages, which causes degradation over time of the insulation for the floating gate.

NAND flash when used with direct addressing will have write failures after tens of thousands of cycles. The solution for this is wear leveling, where the physical location of a block of data is moved on every write. This avoids having frequently written blocks, such as OS file directories, wearing out before the blocks that are rarely written to. There are additional enhancements to this to ensure that blocks that are ‘static’ are also moved periodically to use their physical locations as well for necessary write operations, thus spreading around the load.

The relocation and remapping of blocks requires the implementation of fairly complex algorithms. Designers have a choice of using the system CPU for this or offloading the job to a dedicated controller. There are a series of trade offs in the selection of raw NAND, managed by the system CPU, versus a hardware wear leveling and block management solution like what is found in eMMC.

Interestingly, I backed a Kickstarter for the NEEO, a home automation controller, that just posted a blog about a delay in their system design. They had opted for raw NAND in their prototypes but started seeing failures after continuous stress testing. Early on, a potential investor had casually remarked that they ought to look at eMMC. They say in their blog that they owe them a dinner.

Designing embedded controllers for SD and eMMC requires making a number of choices and selection of the proper IP for the protocols that need to be supported. Cadence recently posted a video on their White Board Wednesday video series that give an overview of the technology available to designers from their IP portfolio. Lou Ternullo, Product Marketing Director in Cadence’s IP Division outlines the various protocols and flash technologies they support.

If you are interested in other areas where Cadence offers IP – and there are quite a few – I suggest looking at their IP Factory Brochure. Also their web site features their IP offerings here.

As for flash memory, it is safe to say that its use will continue to expand. Some day in the future we’ll look back at the idea of keeping our valuable data spinning on mechanical merry-go-rounds at 5,000RPM as quaint and primitive.