WP_Term Object
(
    [term_id] => 15
    [name] => Cadence
    [slug] => cadence
    [term_group] => 0
    [term_taxonomy_id] => 15
    [taxonomy] => category
    [description] => 
    [parent] => 157
    [count] => 487
    [filter] => raw
    [cat_ID] => 15
    [category_count] => 487
    [category_description] => 
    [cat_name] => Cadence
    [category_nicename] => cadence
    [category_parent] => 157
)
            
14173 SemiWiki Banner 800x1001
WP_Term Object
(
    [term_id] => 15
    [name] => Cadence
    [slug] => cadence
    [term_group] => 0
    [term_taxonomy_id] => 15
    [taxonomy] => category
    [description] => 
    [parent] => 157
    [count] => 487
    [filter] => raw
    [cat_ID] => 15
    [category_count] => 487
    [category_description] => 
    [cat_name] => Cadence
    [category_nicename] => cadence
    [category_parent] => 157
)

Cadence 2015 Q2 Results

Cadence 2015 Q2 Results
by Paul McLellan on 07-29-2015 at 6:00 pm

 Let’s start by getting the financial stuff out of the way. Revenue was $416 million; non-GAAP operating margin was 28%; non-GAAP EPS was $0.27; and operating cash flow was $122 million (up at lot, it was just $47M in Q1 and $69M in Q2 of 2014).

The thing that the financial types are most interested in are the changes to Cadence’s stock repurchase program. In CFO Geoff Ribar’s words:We are replacing our current $450 million stock repurchase program with a new program to repurchase $1.2 billion of our shares over the next six quarters through the end of 2016. The actual timing and amount of repurchases will be based on business and market conditions, corporate and regulatory requirements, acquisition opportunities, and other factors. One such factor is the settlement of our warrants which begins in September of this year and extends through early December.

What that all means is that they will repurchase about $1.2B of Cadence stock, mostly during 2016. But readers of Semiwiki are less interested in financial legerdemain than information about product and insight into how the results reflect on market conditions for Cadence’s customers.

Let’s start with geographies and product segments. Geoff Ribar again:Cadence had a strong Q2. Total revenue was $416 million, up 10% compared to $379 million for Q2 of 2014. The revenue mix for the geographies was 48% percent for the Americas; 23% for Asia; 20% for EMEA; and 9% for Japan. Revenue mix by product group was 21% for functional verification; 29% for digital IC design and signoff; 27% for custom IC design; 11% for system interconnect and analysis, and 12% for IP.

In some ways the most impressive number is 12% for IP. Cadence wasn’t really in the IP business until the acquisition of Denali, and even then it only got seriously into the IP business in the last three years since Martin Lund joined from Broadcom in 2012. Synopsys, on the other hand, has been in IP for 25 years and I think it is around 20% of their business (off a larger revenue number, to be fair).


Cadence made two major announcements during the quarter:

  • Genus, which is their next generation synthesis product, already endorsed by Imagination Technologies and Texas Instruments. Like the other -us products, this has been re-architected to take advantage of the availability of large numbers of cores. They claim 5X performance improvement and capability to handle 5 million instances (rough rule of thumb is that an instance is 4 gates so this is roughly 20 million gates)
  • Indago debug platform and three apps:

    • Indago Embedded Software Debug: Resolves bugs associated with embedded software applications by synchronizing software and hardware source code debug
    • Indago Debug Analyzer: Extends root-cause analysis from e testbench (IEEE 1647) to SystemVerilog (IEEE 1800) and increases performance by up to 10X
    • Indago Protocol Debug: Visualizes advanced protocols such as DDR4, ARM AMBA AXI and ACE using Cadence VIP for intuitive debugging

Innovus, the new physical design system, continues to make progress with customers:Qualcomm Technologies, NVIDIA, STMicroelectronics, and Faraday Technology have joined ARM, Freescale, Juniper and others in adopting Innovus for production design at the most advanced nodes, benefiting from excellent quality of results and faster turnaround time.

I still think there is some gamesmanship going on here and that most customers are using multiple physical design systems and are not using any one supplier exclusively. As the dodo says in Alice in Wonderland, “Everyone has won and all shall have prizes.”

Palladium XP won six new logos (no details on who) and a big driver for emulation (in general, not just at Cadence) is dynamic power analysis, especially for mobile. Pre-production testing of their next generation is taking place now, on-track to start shipping before the end of the year.

One interesting area to watch is industry consolidation. NXP and Freescale, Avago and LSI and Broadcom, Tsinghua in China. In the short term this doesn’t have much effect since the contracts are all in place and the number of designs in progress does not change fast. But in the longer term, if the number of companies in the semiconductor ecosystem declines then it might have gradual and negative effect on the EDA and IP industries (and perhaps foundry too). As Lip-Bu said:Long-term impact of this on our industry is complex and difficult to predict. While we do not expect material impact near-term, consolidation could pose a challenge to industry growth over the next few years.

During the Q&A Lip-Bu talked about EUV for a couple of minutes:When you move down to 5-nanometer, clearly double, triple patterning may not be enough. Then you’re starting to really look at the EUV for 5-nanometer from my humble experience in a critical to have EUV. And I’m very pleased to see the ASML, the EUV are making progress. They can go up to 80 watts now and they go up to 500 wafer per day; that is extremely encouraging. Then you’re starting to look at TSMC NTR progress on the EUV side and also some the photo-resist related development. So we keep a very close eye on this whole group maps and the process technology and we also work closely with equipment, semiconductor equipment company to make sure ready.

I think that lost something in the transcription. But the basic facts are what I learned at imec (where Lip-Bu was also attending since he was one of the presenters) that ASML are making significant progress. But there are still major challenges. It is not clear to me if there are any major implications for EUV in EDA, more likely that the implications are if and when we don’t have EUV and have to go to very high numbers of masks for some layers (octuple patterning anyone?).

Cadence has been hiring. They had a shutdown in July 4th week (which was the last week of Q2 for them). But:we’re continuing to add engineering headcount and technical sales headcount. All we want to be clear is that when we leave 2015, we are going to be at a higher expense rate than we were during the beginning of the year.

Transcript of the call on SeekingAlpha is here.

Share this post via:

Comments

0 Replies to “Cadence 2015 Q2 Results”

You must register or log in to view/post comments.