On Tuesday Cadence made a big announcement about their new physical implementation offering, Innovus, during the keynote address at the CDNLive event in Silicon Valley. Cadence CEO Lip-Bu Tan alluded to it during his kick off talk, and next up Anirudh Devgan, Senior Vice President, Digital & Signoff Group, filled in more of the details. I was fortunate enough to have a briefing with Anirudh and Cadence Marketing Director Rahul Deokar on Innovus before the public announcement.
Before I go into the details, I’d like to talk about my experiences with new EDA products. Over the years I have held sales and marketing positions at Cadence and Mentor as well as at smaller companies. In these roles I talked to a lot of customers, and certain themes came up over and over again. The cost of moving to new tools is high; there are risks and the results of moving need to justify the time and effort required. Thus management and engineers will only switch if the benefits are significant, or address a new and otherwise unmanageable design issue.
Usually new tools offer either a turnaround time (TAT) advantage or an improved quality of result, such as performance, power and area (PPA), but not both. Lastly new products were often announced before challenging real world designs had been thrown at them. Now let’s talk about Innovus.
Innovus adds a new placer technology called GigaPlace. This rounds out their updated implementation technology by complementing GigaOpt, Tempus and NanoRoute. Placement is crucial for optimal design results. During his keynote presentation even Anirudh telegraphed that they concurred placement was a weak spot for them previously. He has had 2 years to improve on the technology he inherited when he took over the implementation flow.
In Innovus they are capitalizing on the technology from their Azuro acquisition by incorporating Clock Concurrent Optimization (CCOpt) in the flow. Azuro technology was always strong, but when it was being sold standalone the integration hurdles made for a difficult sale. I know I was there. But with this technology fully integrated with the rest of the P&R flow, using it is much easier. Plus Cadence has polished the useful skew technology that Azuro was starting to roll out at the time of the acquisition. For the clocks, they are using a hybrid approach with H-trees at the higher levels to maintain symmetry, but break out into classic CTS based clocks at lower levels. The portions that are H-tree based help reduce variation induced clock timing issues.
The other big integration for Innovus is with Tempus, the Cadence sign off solution. Faster sign off is an obvious win with direct database integration. But Anirudh also talked about sign off based ECO’s. These are made more efficient because they can be done without tool iterations.
Touting what Cadence calls massively parallel computing, Innovus is said to be able to work on much larger data sets and do so much more quickly. One way to gain from this is to take advantage of larger gate counts in blocks. Cadence is saying it works well with 5-10M or more instance block sizes. This reduces the number of blocks, removing channel routing areas and reducing congestion. These larger blocks will run faster in Innovus too. See the table they provided below for their numbers.
From the chart it seems that there is a bigger win at 28nm than at 16nm, but this is understandable in that 16nm designs have many more constraints, and variation effects grow with additional masks and patterning requirements.
But what about quality of results? Cadence provided the above chart to show improvement in PPA. One of the most interesting aspects of improved TAT and PPA is that designers might have time to improve their designs beyond specs, if they can reach initial design targets faster and then have more iterations available in the time remaining before tape out. One example Cadence cited shows this being done by one of their beta customers.
Speaking of beta customers, it seems Cadence has been working with many of their customers on this technology. They are able to point to numerous design examples and have customer endorsements from the likes of ARM, Freescale, Juniper, Renesas, Spreadtrum and Maxlinear. An impressive list indeed.
Anirudh spoke about how chip companies are no longer easily divided along the lines of Analog or Digital. Today’s SOC’s are predominantly mixed signal. This means that a winning flow will easily allow analog and digital content to be integrated and optimized together. Leveraging Cadence’s strength in analog design, they have added hooks to integrate Virtuoso and Innovus together in the flow. This includes a common database and adds a GUI that uses Tcl for scripting.
Cadence appears to have addressed the main objection to moving to a new tool – will the change provide sufficient benefit to warrant the cost of moving? They seem have their ducks in a row regarding having enough miles under their belt before rolling out a new major update. ARM in particular talked very positively about their results with Innovus on their high end Cortex-A72 core implementation. And Cadence went to lengths to assure me that even for older nodes, all the technology and PDK information will still work. This means that now not only will this be useful for cutting edge designs, but it will also be helpful on a lot of IoT and mobile based designs that must have the lowest possible power and are implemented on nodes ranging from 180nm down to 40nm.
For more information go to theCadence Innovus page.