Embracing the Chiplet Journey: The Shift to Chiplet-Based Architectures

The semiconductor industry is facing a paradigm shift. Traditional scaling, once driven by Moore’s Law, is slowing down. For years, moving to smaller process nodes led to lower transistor costs and better performance. However, scaling from node to node now offers fewer benefits as wafer costs rise much more than the historical 10% with each new node. This, combined with the physical limits of silicon, makes traditional scaling increasingly unviable. This reality is driving the need for new approaches, with chiplet-based architectures emerging as a solution.

The chiplet-based approach offers significant advantages, including modularity for faster and cost-effective design, customization for meeting specific performance and power needs, improved yield by reducing complexity, optimized power and performance through tailored IP integration, and scalability that allows for seamless upgrades without full-chip redesigns.

Boyd Phelps, Senior VP and GM, Silicon Solutions Group, Cadence, gave a keynote presentation at the Chiplet Summit 2025 conference. His talk addressed how the industry is embracing the chiplet journey, the driving factors for rapid adoption, and how Cadence is bringing value to its customer base.

The Rise of Packaging Technology

Packaging technology is now at the forefront of semiconductor innovation. Foundries are investing 10% or more of their R&D capital in advanced packaging techniques. With innovations in 3D packaging, chiplet designs are now becoming viable. These designs offer more flexibility, allowing chiplets from different vendors to be seamlessly integrated into a system, creating a new level of abstraction in chip design.

Next-generation packaging technologies, such as fine-pitch hybrid bonding interconnects (HBI) and through-silicon vias (TSVs), enable further chiplet disaggregation. These technologies allow for ultra-fine interconnects of 3µm, 6µm, and 9µm between stacked dies, eliminating the need for soldered connections. This innovation not only enhances power efficiency and signal integrity but also reduces overall system complexity.

The Demand for Custom Silicon

The demand for custom silicon is being driven by the growing needs of data centers, where fixed power budgets must be balanced with ever-increasing performance demands. Chiplets provide a power-efficient solution for custom silicon, allowing specific functionalities to be tailored for different workloads. This is crucial as industries like automotive, aerospace and defense, and consumer electronics also experience rapid disruption and transformations.

Streamlining Chiplet Design with Pre-Designed Frameworks

At Cadence, the shift to chiplet-based designs is aided by pre-designed chiplet frameworks that allow engineers to quickly select and integrate the right chiplets for various applications. These frameworks reduce design time, enabling faster time-to-market for custom silicon solutions. This modular approach offers greater flexibility compared to traditional monolithic designs.

Automating Custom Silicon Design

The complexity of chiplet-based design requires automation tools. Cadence’s SoC Cockpit concept represents the future of design automation, providing a seamless framework for managing chiplet-based designs. By integrating system-level planning, verification, and optimization, the SoC Cockpit enables efficient chiplet integration, reducing design complexity and accelerating time-to-market.

By using correct-by-construction tools, the design process is made more efficient, ensuring that the final system meets all performance and safety requirements without the need for manual verification.

Seamless Integration in a Chiplet Ecosystem

Going forward, all intellectual property (IP) will be developed with the chiplet framework in mind. The goal is to ensure seamless integration of chiplets from different vendors into a cohesive system that meets the performance, power, and cost requirements of a wide range of applications. This shift will require new design methodologies, tools, and standards that make it easier to develop and integrate chiplets, enabling a more agile and efficient design process.

Summary

The future of semiconductor design lies in the seamless integration of chiplets. As wafer costs rise and node-to-node scaling slows, chiplet-based architectures offer a flexible, scalable, and cost-effective solution. By automating design processes and adopting chiplet frameworks, semiconductor companies can meet the growing demands of industries like data centers, automotive, and consumer electronics, ushering in a new era of innovation in semiconductor solutions.

More information on Cadence’s silicon solutions for accelerating next-generation chiplets and SoCs can be found here. To learn about Cadence’s full suite of tools, methodologies and IP to support your chiplet journey, visit this page.

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