Cadence Sigrity, Together At Last

In July Cadence acquired Sigrity, one of the leaders in PCB and IC packaging analysis. Until a decade ago, signal integrity and power analysis was something that only IC designers needed to worry about. For all except the highest performance boards, relatively simple tools were sufficient. Provided you hooked up the pins on all the packages correctly then the design would work. That is no longer the case and for this reason Sigrity created their product line and subsequently Cadence acquired them.

When I was at Cadence we acquired Cadmos, who were the leader in IC signal integrity at the time. One of the challenges with an acquisitions like Cadmos and Sigrity is that there are really two things involved: a running business and a core technology. Going forward, two things need to be done: ramp up the running business, and integrate the core technology into other existing products. The reason that it is such a challenge is that there is only one team in place that understands the product well enough to do these things, and they are stretched thin to do both. Although it is still work-in-progress, Cadence have come a long way to getting the Sigrity products integrated into Allegro.

By November, Cadence had the Sigrity tools (Power Aware SI, Serial Link SI, Power Integrity, and Package Extraction) updated with Cadence look and feel and available through standard Cadence contracts. Now, in January, Cadence has Sigrity integrated into their high-end Allegro board design suite so that Sigrity products can be used directly from within the Allegro environment.

Capabilities to address something like signal integrity typically show up first as verification tools to check a design has no problems, and allowing the designer to manually fix up the handful of things that get identified. The trouble is that design constraints never get any easier and so verification on its own is not enough. When it is no longer a handful of things that get identified as problems but hundreds or thousands then the technology needs to get integrated into the core algorithms to enable constraint-based design. It is no longer good enough to identify problems, it is necessary to avoid creating them in the first place.

The most critical and highest speed signals on a board these days are typically high-speed serial links. These run at multi-gigabit/s speeds, fast enough to require special analysis that almost goes back to Maxwell’s equations: a full-wave 3D field solver. The board, package and system cannot be analyzed separately, the entire system including the board, multiple packages and multiple chips, and maybe other connectors, must be looked at holistically.

So today Cadence has Allegro Sigrity SI. It is built on top of Allegro PCB/ICP/SiP without requiring any manual translation. It has become an integral piece of the front to back constraint driven PCB/Package design flow, accelerating time to volume manufacturing. Special features allow integrated analysis of high-speed memory interfaces, and very high speed (multi-Gb/s) serial link analysis including algorithmic transceiver model support, an integrated full-wave 3D field solver and a high capacity simulation engine that accurately predicts bit-error-rate. The full Power Integrity Suite is also available for PI signoff (and will be integrated directly into Allegro in the future).