Cadence 3D Methodology

A couple of weeks ago was the 3D Architectures for Semiconductor Integration and Packagingconference in Redwood City. Cadence presented the changes that they have been making to their tool flow to enabled 2.5D (interposer-based) and true 3D TSV-based designs. You know what TSV stands for by now right? Through-silicon-via, a (usually) copper plug that carries signal, power or clock from the front-side of the chip, through the thinned wafer, to the back where it can contact micro-balls on the die or interposer below.

The first people to do 3D designs managed to do it with tools that were unchanged, adding scripts and other modifications to fool the 2D tools into doing their bidding. After all, each die is a 2D design and can, in some sense, be done independently.

One of the biggest changes comes at the front of the design. Even assuming the partition between the different die has already been done (often because they are using different processes, memory or analog on one die, logic on another) there is still a lot that can be done to optimize the 3D structure. Many of the TSVs will end up being used to distribute clock or power with decap capacitors on the interposer. Having too many TSVs drives up the cost (and wastes area) and too few risks reliability failures or intermittent errors.

Since each die is largely designed independently of the others once these decisions have been made, the other big area that needs additional capability is verification. In particular, making sure that all the TSVs on the various die and interposers involved all line up, carry the correct signals and so forth. Not to mention verifying the power delivery network and the clock network behave as planned.

The final big area of difference is manufacturing test. Once the entire design is packaged up there is only access to the pins on the package. These only go to the interposer (in a 2.5D design) or the lowest die (in a 3D design). There is no direct access to the die above. So additional TSVs are required to build a test “elevator” that gets the scan patterns in through the pins and up to the level where they are used. Wafer sort, the forgotten child of manufacturing test, is also much more important in a 3D design due to the “known good die” problem. If a faulty die slips through wafer sort and gets packaged, not only is that die discarded (and it was bad anyway) but other die and interposers (which are most likely good) also get discarded. The cost of a bad die is that much higher than in a normal 2D design.

Of course there are many other issues in 3D other than EDA. It requires a whole new ecosystem and the details of who does what haven’t even all been ironed out yet. TSVs need to be created, wafers need to be thinned, microballs need to be placed, die need to be bonded together, packaged, bonded out, tested. And when all this is done, it needs to be economic to do it for volume production, not just an elegant price-is-no-object technical solution.