Subsystem IP, myth or reality?

I have participated to a panel during IP-SoC, I must say that “Subsystem IP, myth or Reality” was a great moment. The panel was a mix of mid-size IP vendor (CAST, Sonics), one large EDA (Martin Lund from Cadence), Semiwiki blogger and one large IDM (Peter Hirt from STM) who has very well represented the customer side. And, to make the panel even more efficient, the audience was great, with Joachim Kunkel from Synopsys and Philippe Quiniot, STM Group VP, IP Sourcing & Strategy, or Marc Miller, VP Marketing for Tabula, to name a few very active participants.

There are many ways to introduce such a question; I propose to start with my first slide, just to position the problem. Subsystem IP is a great idea, I am sure everybody will agree with the concept, but could it be another one of this great story which end up falling, like Transputer, Gate Array integrating FPGA or Structured ASIC IP Platform? If you prefer to position the problem in a positive way: how should the industry proceed (I mean, vendors AND customers) in order to keep this Subsystem IP alive and growing?

Hal Barbour and Bill finch from CAST have decided to be specific, and to talk about “Platform” instead of Subsystem IP, and have taken a “CPU Subsystem” as an example. I am not sure that I agree with the “Platform” concept, but I must say that some of the Subsystem IP are CPU based, like for example the “ARC based sound system IP” from Synopsys. Why do I am not convinced by Platform for an IP vendor? Just platform sounds to me like a frozen system, and this probably means a lack of flexibility, and something which is “over-designed” if to be used by a variety of customers. Some of these customers will pay for extra gates that they don’t use…

To immediately answer to my objection, I am sharing with you a slide presented by Philippe Quiniot during the morning keynotes, and this picture clearly shows that STM think they should go toward Unified Platform development! Nevertheless, you should notice that these platforms will be developed by STM, for STM internal product group needs… In other words, STM does not expect any IP vendor to provide such a complex, and complete, platform…

Sonics has proposed a view of Subsystem IP which is more Application Specific, showing the Integration trends for Smartphones and Tablets, extracted from a Gartner report. This picture could be representative of the roadmap of the various chip makers addressing this market segment (it’s a bit early to know if integration will effectively happen this way, right?), but it can be used to raise one of the next big question which has been debated during the panel, differentiation.

Imagine that you are an IP vendor who decides to trust Gartner and build various Subsystem IP according with this roadmap, then go to sell these products to the chip makers active in Smartphone and Tablets segments… you may be successful with the companies developing me-too products. But the leaders, the Qualcomm, Nvidia, STM, will tell you that what they expect, above right performance and good deliverables, supposed to be their basic needs, is differentiation.

As mentioned by Peter Hirt “It’s all about differentiation”, and “Subsystems developed by IP vendors are available to everybody”. And conclude the slide by saying that “…Customer may select subset of Subsystem…” The important word here is “subset”! That means that an IP vendor may decide to develop a complete subsystem, to prove being a competence center for a given area, but may end-up selling only a subset.

We should link this comment with the very interesting assertion made by Martin Lund (made during the morning keynotes, and again during the panel): IP reuse is an Oxymoron and Fallacious!

That Martin did say is that Cadence has never sold exactly the same version of an IP function to two different customers, and this was, by the way, confirmed by other IP vendors. Why? Because customers need to differentiate, and to do it, they will always need highly configurable IP. Does that mean that Subsystem IP concept is dead? Not at all, but be sure it will be configurable enough to allow differentiation!

Finally, I will end up with my last slide (above), trying to remind some of the basics if you want to build a Subsystem IP business case. About the reasons why great ideas like Transputer or ASIC integrating FPGA blocs have failed in the past: Moore’s Law for Transputer, as it was possible to build very complexes CPU a few years later, and over-cost for the second great idea. So we could add “Lack of Differentiation” for Subsystem IP, if IP vendors forget to insert high configurability to allow for differentiation…

When I told you that this was a great panel, you can trust me, or read this extract from an Email of Hal Barbour, who has organized the panel, “I received numerous compliments from audience members of how great the panel discussion was. And I spoke to Gabriele this morning and she also told me that use had heard favorable comments too. It was clear that we had a group of people that were experts in this subject matter…”

Eric Esteve from IPNEST