Tag: subsystem

Webinar: EV Subsystem and Vehicle Validation Using MIL and HIL

Webinar: EV Subsystem and Vehicle Validation Using MIL and HIL
by Admin on 10-25-2023 at 2:48 pm

TIME:
NOVEMBER 1, 2023
3:00 PM IST

Venue:
Virtual

About this Webinar

This webinar will focus on how Ansys ROM technology enables component behavior extraction for integration into sub-systems and system validation. We will discover how the twin builder model is integrated for MIL, HIL, and virtual drive validation.

What You

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Nine Cost Considerations to Keep IP Relevant –Part2

Nine Cost Considerations to Keep IP Relevant –Part2
by Pawan Fangaria on 10-06-2015 at 7:00 am
Categories: EDA, IP, Semiconductor Services

In the first part of this article I wrote about four types of costs which must be considered when an IP goes through design differentiation, customization, characterization, and selection and evaluation for acquisition. In this part of the article, I will discuss about the other five types of costs which must be considered to enhance… Read More

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The Earth is Not Flat; Neither is IP

The Earth is Not Flat; Neither is IP
by Paul McLellan on 03-29-2015 at 7:00 pm
Categories: EDA, Perforce

Chip design is largely about assembling pre-designed IP, either developed in other groups in the same company, or brought in from a 3rd party, or occasionally developed within the SoC design group itself. But that makes it sound like it is a bunch of blocks linked together with some interconnect, but of course another important … Read More

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Innovative MIPI Display Solution for UHD Mobile Devices

Innovative MIPI Display Solution for UHD Mobile Devices
by Pawan Fangaria on 03-25-2015 at 7:00 pm
Categories: EDA, IP, Synopsys

Today an SoC cannot be without multiple IP blocks integrated together in the most optimal manner. In such an environment, it’s natural that interoperability and configurability of an IP get prime considerations to achieve the best PPA (Power, Performance and Area) for the SoC containing that IP. While PPA is a basic criterion … Read More

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Prototyping Kits to Accelerate IP Development & Integration into SoCs

Prototyping Kits to Accelerate IP Development & Integration into SoCs
by Pawan Fangaria on 01-04-2015 at 10:00 am
Categories: EDA, IP, Synopsys

With growing SoC size, complexity, software and hardware content in it and shrinking time-to-market, the SoC design completion in time has become increasingly dependent on IP which need to be sourced (internally or externally), customized according to the design need and integrated together into the SoC. While IP providers… Read More

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Subsystem IP, myth or reality?

Subsystem IP, myth or reality?
by Eric Esteve on 12-07-2012 at 5:00 am
Categories: Cadence, IP

I have participated to a panel during IP-SoC, I must say that “Subsystem IP, myth or Reality” was a great moment. The panel was a mix of mid-size IP vendor (CAST, Sonics), one large EDA (Martin Lund from Cadence), Semiwiki blogger and one large IDM (Peter Hirt from STM) who has very well represented the customer side. And, to make the… Read More

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Audio IP Subsystems Made Easy with a Complete, SoC-Ready Solution

Audio IP Subsystems Made Easy with a Complete, SoC-Ready Solution
by Eric Esteve on 04-22-2012 at 12:22 pm
Categories: IP, Synopsys

After the launch of ARC based complete sound system IP by Synopsys last month, which could be the effective starting point for subsystem IP offering, providing the initiative will be successful (this was not really the case in the past, as we discussed it in our blog), the company proposes a webinar focusing on:

  • The growing complexity
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