John Stabenow – introduction
Variability and LDE while process nodes get smaller.
Vinod Kariat – Cadence fellow, R&D, advanced node challenges
Tom Volden – 16 year Cadence veteran, LDE
Francois Lemery – ST, CAD manager
Vinod Kariat – Cadence fellow. Today IC design is driven by Applications, video, mobility, cloud and green tech.
– we need more power efficiency, so will advanced nodes help us?
– Would 28nm be in use for many years? Faster ramp to 20nm than expected.
– Challenge: Foundry and Design costs are high for 22/20nm node. EDA costs like $800M to $1B. Fab costs of $4B.
– Manufacturing: Double Patterning, LDE, New Interconnect Layers, Difficult Design Rules, Device Variation, New Transistors.
– Design challenges: multi source IP, AMS, 3D IC, System In Package.
– LDE: Well Proximity Effects show 24dB difference based on location. How do I know my circuit performance before I have any layout?
John Stabenow – the traditional IC layout flow, which is a serial flow, you don’t know the layout effects until the end of the flow.
What’s new? Prototype layout generation is the new approach using ModGen. Instead of a sequential, slow loop, do smaller, quicker loops.
Demo – LDE sensitivity by using device models from the foundry. Setting constraints to hep generate layout quicker. Analog Design Environment used in the demo. Started up a circuit simulation where design specs are entered into a spreadsheet, but no layout was done yet. Sensitivity Analysis was run for LDE, like Well Proximity Effect (WPE). 61 different points were run, taking about 10 minutes wall time. Results of Sensitivity Analysis shows graphically which MOS devices are most sensitive, uncovered a design problem.
– Adding constraints using Circuit Prospector. The Rapid Analog Prototype can create automatic constraints. In this circuit 19 constraints were auto generated. Constraints for ModGen were also auto generated. ModGen result shown for an MOS instance where you can quickly change the layout finger patterns, adding a guard ring, etc. Now that ModGens were used for MOS instances, this supplies quick feedback on layout so that LDE on an extracted layout can be simulated. A partial layout can be viewed, so that we can see spacing for WPE effects. (had some technical demo issues during live try)
– Compare initial circuit simulation results with no layout versus prototype layout, then find out which MOS devices have the LDE sensitivity. Easy to move layout to reduce LDE sensitivity.
ST 20nm Constraint Driven Modgen Flow
– Must generate an IC floorplan as soon as possible to take into account Stress, WPE, etc.
– Automatic redo (incremental) in case of PDK change based on constraint defintion. Use Pcells, automatic placer, automatic routers.
– Use Modgen with Placer & PIn to trunk router. Modgen lets you group different Pcells together, where placement is DRC aware, and a structured router.
New design flow for 20nm in Virtuoso XL. Device stress extraction of LDE is a non-Cadence tool.
Used Circuit Prospector with Constraint Manager. Added their own experience to extend the Cadence tools. ST created their own Modgen generators.
The days of hand layout for 20nm IC design and the sequential proces of schematics to layout to extraction to simulation are becoming a memory, while using generators to automate IC layout continue to grow. Cadence has a rich history with Skill-based Pcells and the rest of the industry has similar but competing technology based on Pycells, so the marketplace gets to ultimately decide which approach prevails or if both approaches continue to grow.