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A Chat with John Stabenow

A Chat with John Stabenow
by Daniel Payne on 03-20-2012 at 10:57 am

John Stabenow is the marketing group director at Cadence for the Virtuoso products and it has been awhile since we last talked, so we met for lunch on Friday at McMenamins in a city called West Linn, half-way between where we both live in Oregon. I had blogged about Interoperability at DAC 2010 and we had a public exchange at Chip Design Magazine. This time we had a wide ranging discussion on IC topics.

Q: What’s new in IC EDA these days?
A: One new thing is from Orora, a start-up in Seattle, they have an analog model generation tool called Arana that looks interesting. You provide it a transistor-level netlist and it produces an Analog Behavioral Model (ABM) out. ST is an early user. Dr. Richard Shi is the founder.

Q: What tools does Cadence offer for generating analog models?
A: We have something called Schematic Model Generator (SMG).

Q: Why are analog models so important?
A: There’s a great need to abstract analog behavior into higher-level models that can be quickly and accurately simulated, because you cannot SPICE everything you want in a short enough time.

Q: What did you learn from the Neolinear acquisition since 2004?
A: That analog synthesis and analog layout synthesis is very difficult.

Q: What benefit will Synopsys have after acquiring Magma?
A: They can recover some of the simulation customers lost to FineSIM and P&R tools. They also need to decide which IC layout tools survive: IC Designer (a Virtuoso clone) or Magma Titan? Magma probably has more IC layout design customers than Synopsys does.

Q: As the technology nodes get smaller, what issues are your IC customers experiencing?
A: Layout Dependent Effects (LDE) is a growing area of concern in IC design. Transistor performance now depends on what is placed next to each MOS device. You need more than just DRC rules, you need some automation that can be used by a circuit designer first. We will never eliminate the IC layout designer job.

Q: How is your relationship with ClioSoft?
A: They are a great Hardware Configuration Management (HCM) partner, their product is well liked and highly regarded by customers, it’s very complimentary with Virtuoso. IC Manage and Methodics are other HCM vendors. Data management for analog asks the basic question, “What changed on my schematic or layout?” Digital data management is quite different because they look at their task as one of software source code management mostly.

Q: Does Cadence create analog IP for sale?
A: Yes, we have an analog IP design group in Columbia, MD that provides that service. They use Virtuoso tools and tell us unfiltered what they think. Their customers don’t reveal their identities.

Q: What is your take on Carl Icahn raiding Mentor Graphics?
A: My personal opinion is that it would be a mistake to breakup Mentor into pieces.

Q: Is EDA360 still alive now that John Bruggeman left Cadence?
A: We’ve organized our product marketing people back into the business units now, instead of having them centralized. I wish John all the best. CDNLive is not promoting the EDA360 banner front and center.

Q: What were some of the highlights of CDNLive last week?
A: The GLOBALFOUNDRIES 28nm reference flow was a highlight. Freescale did a paper on LDE. Other customers presenting on the IC side include: IBM, Maxim, LSI and TSMC. ADI had a paper on using Circuit Prospector for design reuse and they showed how design constraints could be automated in just seconds. Orora has a paper on the second day showing how an AMS design optimization was reduced from 6 days to just 6 minutes.

Summary

I learn so much when I talk to a seasoned EDA executive like John Stabenow, and look forward to blogging more about how Cadence works with foundries on advanced nodes like 20nm to ensure that the tools, PDKs and methodology are in place to create successful IC designs.

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