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Chip Power Models

Chip Power Models
by Paul McLellan on 05-04-2011 at 4:21 pm

 As the complexity of the chip-package-system (CPS) interactions has increased, the tradeoffs in doing a power and noise analysis has had to gradually increase. As is so often the case in semiconductor designs, issues first arise as second-order effects that can largely be ignored but each process node makes the problem worse so that it can no longer be ignored.

Traditionally, CPS co-analysis and co-optimization lacked accuracy and limited productivity. Analysis was done using heuristic-based models of the die or used certain assumptions such as the lumped Cdie/Rdie numbers. Without a good model of the die, the only way to do a reasonable analysis was to provide artwork from the package and PCB to the chip level designers so that they could model the full-chip along with an appropriate amount of the off-chip interconnect. But these simulations were very time consuming making CPS convergence difficult. What was required was a good chip power model so that the package and board engineers could iterate their part of the design independently and with a much quicker iteration time.

Apache introduced their CPM as a die modeling technology in 2006. It leverages full-chip time domain and AC analysis technologies to create a compact and highly accurate electrical representation of the chip in various operating modes. It models the entire die power delivery network (PDN) including device level (switching, leakage) and parasitic information to create a SPICE-based model with ports at the die level bumps or pads. It accurately represented the electric response of the chip for a wide range of frequencies from DC to multi-GHz.

CPM 2.0 is Apache’s second generation of this modeling technology. It models the operation of the chip in a manner that causes additional stress for the system PDN, in particular taking into account resonance frequencies in the PDN. These are increasingly important in nodes below 40nm. This allows package and board engineers to view the impact of their design changes deep inside the chip.

 PDN analysis must use both frequency and time domain simulations. Frequency domain simulations are used to understand the various resonance point of the combined PDN and ensure the system impedance does not get too high. It is not feasible to do a full analysis on a modern chip but CPM 2.0 addresses this issue by including a resonance-aware mode in which current signatures are deliberately picked around the CPS resonance frequency. This is in contrast to CPM 1.0 which targeted the scenario with highest power consumption. But the two are not the same.

Variable power features are used to model transients on the chip, such as when the chip moves from one clock-gating mode to another, when power-down areas are powered on and so on. The CPM provides stress mode coverage of these potentially significant events.

Apache CPM white paper

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