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SoC Power Integrity Challenges

SoC Power Integrity Challenges
by Daniel Payne on 04-08-2013 at 4:46 pm

At DAC in 2012 I visited a few dozen EDA companies and blogged 32 articles, however I didn’t get to see what Apache Design (now a subsidiary of ANSYS) had to say. I did have 20 minutes today to watch their latest video on SoC Power Integrity Challenges and decided to share what I learned. If you want to watch the video at Tech Online, then they will require you to register or login.
Arvind Shanmugavel, Director of Applications Engineering hosted the video.

The big picture challenges in IC design were identified as:

  • Integration and cost factors
  • Power and performance goals
  • Form-factor requirements

My personal use of an iPad and 17″ MacBook Pro convince me that power and performance requirements really drive these consumer products, because both can get warm while playing YouTube videos and even Apple recommends that you NOT place the MacBook Pro on your lap to avoid discomfort or burns.

What would you ideally need for SoC power integrity? Three things to start with:

  • The capacity to simulate the entire SoC placed in a package, mounted on a board.
  • Analytical results for power, signal EM (electro-migration)
  • Accuracy compared to silicon measurements

As an SoC operates the logic, memory and other IP blocks create a wide range of current consumption values that are based on process, voltage, temperature and specific input stimulus. If you can start to get power estimates at the RTL design stage, then you can start making power grid design choices and even begin to optimize for power before the IC has been implemented.

As IC implementation takes place you have to begin modeling the Power Deliver Network (PDN) including both the SoC and its package using both s-parameters and RLC interconnect. Choosing which vectors create the maximum current peaks is essential to understanding worst case power demands.

Low-power chips use many power-saving modes to meet requirements and companies like ARM publish how-to guides for managing low-power with their A-series processors:

  • Full Run Mode
  • Run Mode with MPE disabled
  • RUn Mode with MPE powered off
  • Standby
  • Dormant
  • Shutdown

Voltage drops internal to an SoC depend on both current draw and di/di, the change of current as a function of time. When a shutdown block wakes up it creates an in-rush current, another effect that needs to be simulated.

A designer needs to target specific vectors for each operating mode of the IC and transition between modes. Modeling at the RTL level you can get early vectors identified for your power plan that identify the highest di/dt states. A chip power model (CPM) can then be created for system noise modeling.

One low power techniques is power gating to control power to a block or cell, coarse grain or fine grain:

When using power-gated design you need to analyze for off-state leakage, rush current, differential voltage checks, ramp-up time, noise coupling and switch Id-sat checks.

For best results you must consider analyzing the chip, mounted in a package, connected to a board.

Summary

Apache Design has created a suite of EDA tools that span the Chip, Package and System levels to enable SoC Power Integrity design and analysis. Other EDA companies have historically focused on only one of these design domains at a time, so one big difference with Apache is how they have looked at all three domains at once in terms of power integrity.

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