TSMC will be at DAC again this year, of course. The main event, as last year, is the OIP Theater where TSMC’s partners come and present their collaboration stories. Here is the schedule:… Read More
TSMC Goes To DAC
The Morphing of Intel’s Monopoly
It was a generation ago when Intel, less than three years old, created the three fundamental building blocks of the compute era: the DRAM, the EPROM and the Microprocessor, an incredible feat of innovation by any measure. Manufacturing yield, not power or performance determined success of failure and in the first two … Read More
IP Quality: Foundation of a Successful Ecosystem
Talking about Design IP (I mean successful Design IP) lead you to quickly pronounce the two magic key words: Quality and Ecosystem. Those who remember the IP emergence in the mid 90’s know very well why Quality has to be a prerequisite when dealing with Design IP, as they probably have paid the price of mediocre IP quality at that time.… Read More
How To Design a TSMC 20nm Chip with Cadence Tools
Every process node these days has a new “gotcha” that designers need to be aware of. In some ways this has always been the case but the changes used to be gradual. But now each process node has something discontinuously different. At 20nm the big change is double patterning. At 14/16nm it is FinFET.
Rahul Deokar and John… Read More
Solido CEO on 20nm/16nm TSMC and GLOBALFOUNDRIES Design Challenges
EDA needs more CEOs like Amit Gupta. Solido, which is now profitable, is his second AMS EDA company. The first, Analog Design Automation (ADA), was purchased by Synopsys for a hefty multiplier. Prior to becoming an EDA entrepreneur, Amit was product manager for the wireless group at Nortel and a hardware engineer for the RF communications… Read More
TSMC ♥ Solido
Process variation has been a top trending term since SemiWiki began as a result of the articles, wikis, and white papers posted on the Solido landing page. Last year Solido and TSMC did a webinar together, an article in EETimes, and Solido released a book on the subject. Process variation is a challenge today at 28nm and it gets worse… Read More
Morris Chang on Altera and Intel
If you want to know why I have written so much about TSMC in the past five years here it is: TSMC executives are approachable, personable, answer questions straight on, and have yet to lead me astray. If you want an example of this read the Chairman’s comments on the TSMC Q1 2013 earnings call transcript.
“On 16-nanometer FinFET, we … Read More
Cadence ♥ TSMC
TSMC has been investing in the fabless semiconductor ecosystem for 25+ years and that is why they are the #1 foundry and lead this industry (my opinion). I’m a big fan of joint webinars. Not only is it collaboration open to the masses, it is a close collaboration between the two sponsoring companies. Having worked on the TSMC… Read More
Altera, Intel, TSMC, ARM: the Plot Thickens
Vince Hu of Altera presented us her at the GlobalPress Electronics Summit on their process roadmap. Since just a month or two ago they announced that Intel would be their foundry at 14nm, everyone wanted to get a better idea of what was really going on.
At 28nm, Altera use 2 processes, TSMC 28HP (for high end Stratix-5 devices) and TSMC… Read More
Two New TSMC-Cadence Webinars for Advanced Node Design
Foundries and EDA vendors are cooperating at increasing levels of technical intimacy as we head to the 20nm and lower nodes. Cadence has a strong position in the EDA tools used for IC design and layout of custom and AMS (Analog Mixed-Signal) designs. They have created a series of webinars to highlight the design challenges and new… Read More