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TSMC Banner 2023
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Certus Semiconductor at the 2025 Design Automation Conference #62DAC

Certus Semiconductor at the 2025 Design Automation Conference #62DAC
by Daniel Nenni on 06-15-2025 at 10:00 am

62nd DAC SemiWiki

Certus Semiconductor Brings High-Performance Custom I/O and ESD IP to DAC 2025

Certus Semiconductor, a trusted leader in custom I/O and ESD solutions, will exhibit at booth #1731 during DAC 2025, June 23–27 in San Francisco. Known for its robust, customer-proven IP tailored for challenging applications, Certus will highlight… Read More


Alchip’s Technology and Global Talent Strategy Deliver Record Growth

Alchip’s Technology and Global Talent Strategy Deliver Record Growth
by Kalar Rajendiran on 05-20-2025 at 10:00 am

Alchip TSMC 2nm N2

Alchip Technologies Ltd., a global leader in high-performance computing (HPC) and artificial intelligence (AI) ASIC design and production services, continues its trajectory of rapid growth and technical leadership by pushing the boundaries of advanced-node silicon, expanding its global design capabilities, and building… Read More


Analog Bits Steals the Show with Working IP on TSMC 3nm and 2nm and a New Design Strategy

Analog Bits Steals the Show with Working IP on TSMC 3nm and 2nm and a New Design Strategy
by Mike Gianfagna on 05-09-2025 at 8:00 am

Analog Bits Steals the Show with Working IP on TSMC 3nm and 2nm and a New Design Strategy

The TSMC Technology Symposium recently kicked off in Santa Clara, with a series of events scheduled around the world. This event showcases the latest TSMC technology. It is also an opportunity for TSMC’s vast ecosystem to demonstrate commercial application on TSMC’s technology. There is a lot to unpack at an event like this. There… Read More


TSMC Describes Technology Innovation Beyond A14

TSMC Describes Technology Innovation Beyond A14
by Mike Gianfagna on 05-01-2025 at 10:00 am

Device Architecture Outlook

The inaugural event for the 2025 TSMC Technology Symposium recently concluded in Santa Clara, California. This will be followed by events around the world over the next two months. We have summarized information from this event regarding process technology innovation and advanced packaging innovation. Overall, the A14 process… Read More


TSMC Brings Packaging Center Stage with Silicon

TSMC Brings Packaging Center Stage with Silicon
by Mike Gianfagna on 04-23-2025 at 11:45 am

TSMC Brings Packaging Center Stage with Silicon

The worldwide TSMC 2025 Technology Symposium recently kicked off with the first event in Santa Clara, California. These events typically focus on TSMC’s process technology and vast ecosystem. These items were certainly a focus for this year’s event as well. But there is now an additional item that shares the spotlight – packaging… Read More


TSMC 2025 Technical Symposium Briefing

TSMC 2025 Technical Symposium Briefing
by Daniel Nenni on 04-23-2025 at 11:40 am

TSMC Advanced Tecnology RoadMap 2025 SemiWiki

At the pre-conference briefing, Dr. Kevin Zhang gave quite a few of us media types an overview of what will be highlighted at the 2025 TSMC Technical Symposium here in Silicon Valley. Since most of the semiconductor media are not local this was a very nice thing to do. I will be at the conference and will write more tomorrow after the … Read More


IEDM 2025 – TSMC 2nm Process Disclosure – How Does it Measure Up?

IEDM 2025 – TSMC 2nm Process Disclosure – How Does it Measure Up?
by Scotten Jones on 02-10-2025 at 6:00 am

Figure 1

Initial thoughts

At IEDM held in December 2024, TSMC presented: “2nm Platform Technology featuring Energy-efficient Nanosheet Transistors and Interconnects co-optimized with 3DIC for AI, HPC and Mobile SoC Applications,” the authors are:

Geoffrey Yeap, S.S. Lin, H.L. Shang, H.C. Lin, Y.C. Peng, M. Wang, PW Wang, CP Lin, KF… Read More


TSMC Unveils the World’s Most Advanced Logic Technology at IEDM

TSMC Unveils the World’s Most Advanced Logic Technology at IEDM
by Mike Gianfagna on 12-19-2024 at 10:00 am

TSMC Unveils the World’s Most Advanced Logic Technology at IEDM

There was a lot of discussion at IEDM about the coming shift to gate-all-around (GAA) transistor structures. This new device brings many benefits to continue device scaling, both at the monolithic device level as well as for multi-die design. The path to GAA is not simple, there are new material, process and design considerations… Read More


IEDM Opens with a Big Picture Keynote from TSMC’s Yuh-Jier Mii

IEDM Opens with a Big Picture Keynote from TSMC’s Yuh-Jier Mii
by Mike Gianfagna on 12-12-2024 at 10:00 am

IEDM Opens with a Big Picture Keynote from TSMC’s Yuh Jier Mii

The main program for the 70th IEDM opened on Monday morning in San Francisco with an excellent keynote from Dr. Yuh-Jier Mii, Executive Vice President and Co-Chief Operating Officer at TSMC. Dr. Mii joined TSMC in 1994. Since then, he has contributed to the development and manufacturing of advanced CMOS technologies in both fab

Read More

Analog Bits Builds a Road to the Future at TSMC OIP

Analog Bits Builds a Road to the Future at TSMC OIP
by Mike Gianfagna on 10-21-2024 at 6:00 am

Analog Bits Builds a Road to the Future at TSMC OIP

The TSMC Open Innovation Platform (OIP) Ecosystem Forum has become the industry benchmark when it comes to showcasing industry-wide collaboration. The extreme design, integration and packaging demands presented by multi-die, chiplet-based design have raised the bar in terms of required collaboration across the entire … Read More