Banner Electrical Verification The invisible bottleneck in IC design updated 1
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Electronics Production Healthy

Electronics Production Healthy
by Bill Jewell on 09-16-2020 at 4:00 pm

Electronics Production 2020

Global electronics production is healthy, despite the COVID-19 pandemic. The chart below shows the three-month-average change versus a year ago (3/12 change) in electronics production (measured in local currency) for the major Asian producers. China is the largest electronics manufacturing country and the original source… Read More


VLSI Symposium 2020 – Imec Monolithic CFET

VLSI Symposium 2020 – Imec Monolithic CFET
by Scotten Jones on 09-13-2020 at 10:00 am

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The 2020 VLSI Technology Symposium was held as a virtual conference from June 14th through June 19th. At the symposium Imec gave an interesting paper on Monolithic CFET and I had a chance to interview one of the authors, Hiroaki Arimura.

It is well known in the industry that FinFETs (FF) are reaching the end of their scaling life. Samsung… Read More


Could loss of SMIC lead to loss of most of China?

Could loss of SMIC lead to loss of most of China?
by Robert Maire on 09-13-2020 at 6:00 am

SMIC Banned

Is the US finally getting truly tough on China? or just a bluff?
Could lead to a global reset of the industry & 10 year retreat?
Tech stocks wings have melted after super heated stock run?
SMIC added to the “naughty” list?

There have been numerous reports that the US is considering adding SMIC to the China “naughty”… Read More


Online Verification Meet-up With Intel and Arm!

Online Verification Meet-up With Intel and Arm!
by Daniel Nenni on 09-11-2020 at 10:00 am

Online meetup sep semiwiki

Veriest is headquartered in Israel with engineering sites in Serbia & Hungary. The team has accumulated a wealth of experience through involvement in projects in the forefront of semiconductor technology.

Veriest maintains unrivaled quality standards in terms of both service and knowledge. With the ability to take on … Read More


Samtec Delivers Ultra-High Density with Direct Connect™ to IC Package Technology

Samtec Delivers Ultra-High Density with Direct Connect™ to IC Package Technology
by Mike Gianfagna on 09-11-2020 at 6:00 am

Samtec Direct Connect to IC Package Technology

We all know the signal integrity and power integrity challenges of high-performance system design.  It used to be enough to design a robust chip. Now, the interaction between the chip, the substrate/package and the PCB all matter. If your design is 2.5D, as many are these days, the problems just gets worse. Chiplets are becoming… Read More


Alchip at TSMC OIP – Reticle Size Design and Chiplet Capabilities

Alchip at TSMC OIP – Reticle Size Design and Chiplet Capabilities
by Mike Gianfagna on 09-04-2020 at 10:00 am

Alchip machine learning design

This is another installment covering TSMC’s very popular Open Innovation Platform event (OIP), held on August 25. This event presents a diverse and high-impact series of presentations describing how TSMC’s vast ecosystem collaborates with each other and with TSMC.  This presentation is from Alchip, presented by James Huang,… Read More


Can you really meet your SoC design schedule without a good GUI?

Can you really meet your SoC design schedule without a good GUI?
by Daniel Nenni on 08-31-2020 at 10:00 am

flow3 1

Talk to the members of a digital design team and you will always find two types of users. One who likes using the GUI while working on his design and the other who is passionate about using scripts and the command line options. This is akin to the two camps of users who either love either good old Vi/Vim or the ever versatile Emacs editor.… Read More


Techniques to Reduce Timing Violations using Clock Tree Optimizations in Synopsys IC Compiler II

Techniques to Reduce Timing Violations using Clock Tree Optimizations in Synopsys IC Compiler II
by eInfochips on 08-27-2020 at 10:00 am

eInfochips clock flow

The semiconductor industry growth is increasing exponentially with high speed circuits, low power design requirements because of updated and new technology like IOT, Networking chips, AI, Robotics etc.

In lower technology nodes the timing closure becomes a major challenge due to the increase in on-chip variation effect and… Read More


Semiconductors Not as Bad as Expected!

Semiconductors Not as Bad as Expected!
by Bill Jewell on 08-24-2020 at 4:00 pm

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In the early stages of the global COVID-19 pandemic, most forecasters expected the semiconductor market to decline in 2020, including our May Semiconductor Intelligence projection of a 6% drop. However, the semiconductor market has shown surprising strength so far this year. WSTS reported the 2Q 2020 semiconductor market … Read More


Moving to Deeply Scaled Nodes for Power? There is a Better Way

Moving to Deeply Scaled Nodes for Power? There is a Better Way
by Mike Gianfagna on 08-24-2020 at 10:00 am

AGGIOS Definition

Did you know you can save 30% to 60% power without spending a fortune on a process migration? There is a better way than moving to deeply scaled nodes for power. Read on…

Have you heard of AGGIOS? You will. The name stands for AGGregated IO Systems, and a team of ex ARM and Qualcomm engineers are re-inventing power management. I’ll explain… Read More