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I just watched an interesting video of a demonstration at DAC of the eSilicon GDS II online quote for TSMC. Actually, it wasn’t so much as a demonstration as an interactive use of the quote tool using data supplied by a member of the audience.
The quote system works for TSMC processes from 28nm up to 350nm. The design the audience… Read More
eSilicon will be providing books for the first 300 people to attend the Tuesday night networking reception sponsored by SemiWiki. To avoid confusion they will be giving out BOOK COUPONS when you arrive to be redeemed when the event starts so grab a coupon, enjoy the food and drinks! I can assure you this will be the ultimate networking… Read More
One of the things that eSilicon does is handle all the backend operations for the designs that they do. eSilicon is a fabless ASIC company and so the most visible part of the business is the design (not to mention IP which is a critical input into design these days). But another key part is arranging with foundries like TSMC to get the … Read More
eSilicon is a fabless chip company that is credited with starting the fabless ASIC movement. You can read more about them in the ASIC chapter of SemiWiki’s new book on the fabless semiconductor industry. But why would a fabless ASIC company come to DAC?
At one level, eSilicon starts where EDA technology ends – taking a taped out chip… Read More
This weekend I was in the pits for the Flying Lizard Motorsports team at the Monterey Grand Prix. It was an auction item (donated by eSilicon) at EDA’s 50[SUP]th[/SUP] Anniversary party last year, and let me tell you it was an amazing experience and a very interesting story, absolutely. But first let me tell you that if you get a “Hot… Read More
Pop quiz: eSilicon has a big IP development group in what Asian country? If you didn’t know and you guessed, you probably got it wrong with China or India. It is Vietnam. In fact they have two sites. One in Ho Chi Minh City (that used to be called Saigon) and one in Da Nang.
At Electronic Design Process Symposium (EDPS) held last … Read More
On April 18, 2014 in Monterey California there will be a series of discussions on the challenges of IP reuse. These discussions are part of the 2014 Electronic Design Process Symposium (EDPS). Representatives from IP, ASIC, foundry and EDA will weigh in the challenges and issues. Here is a preview of one of the presentations from… Read More
As I blogged about recently, eSilicon have completely automated the quote process for their MPW shuttle service. You can use an online interface that runs in the browser but there is also an app that you can download from the App Store.
So I decided I had a few million dollars to burn and I’d get myself my very own TSMC 20nm parts.… Read More
Every ASIC company has a major challenge: they have to work out what it is going to cost to build the customer’s product and commit to deliver it at that price. Too high and you lose the business. Too low and you will wish you’d lost the business. Historically this has been done largely manually. This is an expensive process.… Read More
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