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At SEMICON West, Applied Materials announced a new selective gap fill tool to address the growing resistance issues in interconnect at small dimensions. I had the opportunity to discuss this new tool and the applications for it with Zhebo Chen global product manager in the Metal Deposition Products group at Applied Materials.… Read More
Summary
At the recent Intel Architecture Day 2020 symposium, a number of technology enhancements to the Intel 10nm process node were introduced. The cumulative effect of these enhancements would provide designs with a performance boost (at iso-power) approaching 20% – a significant intra-node enhancement, to be sure. The… Read More
HCL is an interesting organization. You may know them as an Indian company that provides software and hardware services. At about $10B US and over 110,000 employees working around the world, they are indeed a force in the industry. They’ve also created a software company called HCL Software that develops tools and technologies… Read More
One of the Designer Track at this year’s DAC focused on the popular topic of automotive electronics. The title was particularly on-point, The Modern Automobile: A Safety and Security “Hot Zone”. The session was chaired by Debdeep Mukhopadhyay, a Professor at the Indian Institute of Technology in Kharagpur.
This special, invited… Read More
Every chip needs ESD protection, especially RF, analog and nm designs. Because each type of design has specific needs relating to IOs, pad rings, operating voltage, process, etc. it is important that the ESD protection network is carefully tailored to the design. Also because of interactions between the design and its ESD protection… Read More
Just a little funny history, after I started my Silicon Valley Blog in 2009 several EDA CEOs bullied me into creating my own site to compete with John Cooley’s DeepChip.com. Competition is good, right? One good friend and CEO even suggested I call it DeepNenni.com. Thankfully we came up with something a little less awkward,
There was a “research reviewed” panel on Thursday at DAC entitled Shortening the Wires Between High-Level Synthesis and Logic Synthesis. Chaired by Alric Althoff of Tortuga Logic, the panel explored methods to deal with wire delays in high-level synthesis and logic synthesis. The four speakers and their focus were:
Artificial Intelligence (AI) and Machine Learning (ML) are becoming more and more commonplace in our world. We have Siri, Alexa and Google Assistant that understand our voice commands. Vision systems that recognize objects are used for facial recognition, autonomous driving, medical, geographical and many other applications.… Read More
On Thursday July 9 Imec held a virtual technology forum. Imec is one of the premier research organizations working on semiconductor technology and their forums are always interesting. My area of interest is process technology and the following are my observation in that area from the forum.
Luc Van Den Hove
Luc Van Den Hove is the… Read More
DAC was full of great panels, research papers and chip design stories this year, the same as other years. Being a virtual show, there were some differences of course. I’ve heard attendance was way up, allowing a lot more folks to experience the technical program. This is likely to be true for a virtual event. I’m sure we’ll see more… Read More
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