All Things Semiconductor!
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Join us on May 31, 2012 for the first in a series of conversations exploring concepts and best practices for emerging companies. The first conversation will outline the critical milestones which must be conquered to take a start-up from early stages… Read More
A perennial DAC highlight for me is the panel session sponsored by Women in Electronic Design. This year, it is called “The Mechanics of Creativity: What does it take to be an idea machine?”
Is this an oxymoron?
I interviewed panelist Dee McCrorey , Chief Risk Guru and Innovation Catalyst at Risktaking for Success LLC, to find out.… Read More
I went to part of the Linley Tech Mobile Conference. This is the current incarnation of what started life as Michael Slater’s Microprocessor Report, and the twice-yearly Microprocessor Forum. These very technical analysis organizations seem to work well when they are a small group of analysts working together to cover… Read More
Image RemovedFor the fourth year Atrenta, Cadence and Springsoft are jointly sponsoring the “I LOVE DAC” campaign. In case you have been hibernating all winter, DAC is June 3-7th in San Francisco at the Moscone Center.
There are two parts to “I LOVE DAC”. First, if you register by May 15th (and they haven’t… Read More
Image RemovedPart I is here.
In the panel session at EDPS on 3D IC a number of major issues got highlighted (highlit?).
The first is the problem of known-good-die (KDG) which is what killed off the promising multi-chip-module approach, perhaps the earliest type of interposer. The KDG problem is that with a single die in a package … Read More
The second day (more like a half-day) of EDPS was devoted to 3D ICs. There was a lot of information, too much to summarize in a few hundred words. The keynote was by Riko Radojcic of Qualcomm, who has been a sort of one-man-band attempting to drive the EDA and manufacturing industries towards 3D. Of course it helps if you don’t … Read More
Image RemovedMike Hutton of Altera spends most of his time thinking about a couple of process generations out. So a lot of what he worries about is not so much the fine-grained architecture of what they put on silicon, but rather how the user is going to get their system implemented. 2014 is predicted to be the year in which over half … Read More
Image RemovedEDPS was last Thursday and Friday in Monterey. I think that this is a conference that more people would benefit from attending. Unlike some other conferences, it is almost entirely focused around user problems rather than doing a deep dive into things of limited interest. Most of the presentations are more like survey… Read More
Image RemovedOnce again DAC has a full program of panel sessions that take place on the exhibit floor at the DAC pavilion, aka booth 310.
Gary Smith kicks off the program with his annual “What’s Hot at DAC” presentation on Monday, June 4th, from 9:15-10:15am. The rest of Monday’s pavilion panels are:
Image RemovedThe technical program for DAC 2012 has an exceptional quality of technical papers, panels, special sessions, WACI (Wild and Crazy Ideas), WIP (Work In Progress), full day tutorials and user-track. The program is tailored for researchers and developers focused on electronic design automation (EDA) and embedded… Read More
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Concerned about IP security threats for your SoCs?
Achronix: Accelerate Data Processing Algorithms using FPGAs with 2D Network-on-Chip
PAVE360: Of SoCs, Digital Twins, and Validating Autonomous Vehicle Behavior
Thermal-induced Reliability Challenges and Solutions for Advanced IC Design
REPLAY: GPU-Powered SPICE: The Way Forward for Analog Simulation
REPLAY: Avoiding CDM (Charged Device Model) ESD Failures
REPLAY: eFPGA – "What a great idea! But I have no idea how I’d use it!"
REPLAY: Ensuring System-level Security Through Hardware/Software Security Verification
REPLAY: Fabless: The Transformation of the Semiconductor Industry
REPLAY: The Brave New World of Customized Memory
REPLAY: Embedded FPGA: The Fabric for Optimized Machine Learning
REPLAY: VLSI Design Methodology Development
REPLAY: Lightspeed Data Sync - Design Workspace Problems Solved!
REPLAY: Desinging Complex SoCs and Dealing with Multiple File Formats?
REPLAY: How ASIC/SoC Prototyping Solutions Can Help You!
REPLAY: Reusing Your IPs & PDKs Successfully With Cadence® Virtuoso®
REPLAY: Taiwan ESD Workshop Recording
REPLAY: Reduce Risk and Improve Quality of AMS IP’s using AI-Powered Automated Timing Arc Prediction
REPLAY: Text: A Year of Breakfast Bytes by Paul McLellan (Free PDF Version)
REPLAY: Finding Your Way Through Verification
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Concerned about IP security threats for your SoCs?
Achronix: Accelerate Data Processing Algorithms using FPGAs with 2D Network-on-Chip
PAVE360: Of SoCs, Digital Twins, and Validating Autonomous Vehicle Behavior
Thermal-induced Reliability Challenges and Solutions for Advanced IC Design
REPLAY: GPU-Powered SPICE: The Way Forward for Analog Simulation
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REPLAY: eFPGA – “What a great idea! But I have no idea how I’d use it!”
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REPLAY: The Brave New World of Customized Memory
REPLAY: Embedded FPGA: The Fabric for Optimized Machine Learning
REPLAY: VLSI Design Methodology Development
REPLAY: Lightspeed Data Sync – Design Workspace Problems Solved!
REPLAY: Desinging Complex SoCs and Dealing with Multiple File Formats?
REPLAY: How ASIC/SoC Prototyping Solutions Can Help You!
REPLAY: Reusing Your IPs & PDKs Successfully With Cadence® Virtuoso®
REPLAY: Taiwan ESD Workshop Recording
REPLAY: Reduce Risk and Improve Quality of AMS IP’s using AI-Powered Automated Timing Arc Prediction
REPLAY: Text: A Year of Breakfast Bytes by Paul McLellan (Free PDF Version)
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[Forum] => vw\vw\XF\Entity\Forum Object
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[populated:protected] => 1
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better_recent_comments-2
Widget_Better_Recent_Comments Instance: 2Array
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[avatar] =>
[date] => 1
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[display_widget_mobile] => 1
[rw_opt] => Array
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[others_front_page] => 1
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[rw_opt_exclude] => Array
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Widget_Better_Recent_Comments
Response to IP’s Growing Impact On Yield And Reliability