The industry recently concluded a series of technology events for the all the major foundries. Done as virtual events this year, each one provided a significant update on technology platforms, roadmaps and ecosystem partnerships. These events are quite valuable to chip design teams who need to be aware of the latest in process,… Read More
Webinar: Menta is Breaking New Ground with eFPGA IP Using Adaptive DSP
Menta is a unique embedded FPGA (eFPGA) company. Their eFPGA IP is based completely on standard cells provided by the foundry, the customer or a third party – no custom cells or custom cell characterization is needed. They also don’t require any specific library, process step or metal stack. All this makes Menta’s eFPGA IP easy to… Read More
Silicon Catalyst Hosts Semiconductor Industry Forum – A View to the Future … it’s about what’s next®
Silicon Catalyst has been hosting semiconductor forums since 2018. At these events, a group of industry leaders gathers to discuss trends in the semiconductor industry and what the future may hold as a result. I recently had an opportunity to speak with Pete Rodriguez, CEO at Silicon Catalyst. Pete explained that these forums … Read More
Achieving 112Gbps PAM4 Channels with Achronix FPGAs and Samtec Interconnect
They say that getting there is half the fun. On December 1, Achronix and Samtec will present a webinar on this topic in the context of high-performance front panel to midplane and midplane to backplane channel design. Technology, materials and system design will all be discussed with a focus on achieving 112Gbps PAM4 channels with… Read More
Powering the Next Generation of Hearables and Wearables with Chipus
Chipus is an interesting company. It’s been around since 2008 and focuses on mixed-signal ASICs, intellectual property blocks and IC design services. They are headquartered on the island of Florianopolis, which is described as the most dense startup ecosystem in Brazil. The company has substantial skills in analog and mixed… Read More
Mentor Offers Next Generation DFT with Streaming Scan Network
Design for test (DFT) requires a lot of up-front planning that can be difficult to alter if testing needs or performance differ from initial expectations. Hierarchical methodologies help in many ways including making it easier to reduce on chip resources such as the number of test signals. Also, hierarchical test allows for speed-ups… Read More
Agile and DevOps for Hardware. Keynotes at DVCon Europe
Paul Cunningham (Verification CVP/GM at Cadence) initiated our monthly Innovation in Verification blog to hunt for novel ideas in verification, breaking past the usual steady, necessary but undramatic pace of incremental advances. I attended a couple of sessions from DVCon Europe recently, and was encouraged to hear a couple… Read More
SiFive Expands RISC-V Technology and its Ecosystem at the Fall Linley Processor Conference
As the Linley Fall Processor Conference winds down, there are certain presenting companies that left a lasting impression. SiFive is one of those companies. On October 21, SiFive introduced the newest member of the SiFive Intelligence family of processor coresSiFive Intelligence family of processor cores, based on… Read More
Achronix is Driving the Fourth FPGA Wave
Technology typically evolves in waves. Sometimes it’s referred to as a “revolution” or an “age”. The industrial revolution and the information age are examples. These kinds of categorizations help to clarify the impact of innovation in ways that are relevant to everyone – you can’t look away if the world is changing around you.… Read More
Embedded Systems Development Flow
Earlier this year. as part of my coverage of the virtual Design Automation Conference (DAC), I interviewed Agnisys CEO and founder Anupam Bakshi. He talked about the new products they introduced at the show and filled me in on the history of the company and his own background. Recently, Anupam presented the webinar “System Development… Read More
Flynn Was Right: How a 2003 Warning Foretold Today’s Architectural Pivot