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Synopsys
Posted on

Using HSPICE StatEye to Tackle DDR4 Rail Jitter

Using HSPICE StatEye to Tackle DDR4 Rail Jitter
by Tom Simon on 02-15-2017 at 12:00 pm
Categories: EDA, Synopsys

The world is a risky place, according to Scott Wedge, Principal R&D Engineer at Synopsys, who presented at the Synopsys HSPICE SIG on Feb 2[SUP]nd[/SUP] in Santa Clara. Indeed, the world circuit designers face can be uncertain. Dealing with risk and departure from ideal was a main theme in the fascinating talks at this dinner… Read More

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FPGA Design Gets Real

FPGA Design Gets Real
by Tom Simon on 02-08-2017 at 12:00 pm
Categories: EDA, FPGA, Synopsys

FPGA’s have become an important part of system design. It’s a far cry from how FPGA’s started out – as glue logic between discrete logic devices in the early days of electronic design. Modern day FPGA’s are practically SOC’s in their own right. Frequently they come with embedded processor cores, sophisticated IO cells, DSP,… Read More

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Verifying Design for In-Car Networks

Verifying Design for In-Car Networks
by Bernard Murphy on 02-03-2017 at 7:00 am
Categories: Automotive, EDA, Synopsys

Once upon a time the role of electricity in a car was pretty modest: spark plugs, alternator, lighting, some simple instrumentation and maybe heating, all supported by an equally simple wiring harness (my wife has a 1962 Morris Minor, so I know exactly what the whole wiring harness looks like). How times have changed. Now most or … Read More

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SPIE Advanced Lithography and Synopsys!

SPIE Advanced Lithography and Synopsys!
by Daniel Nenni on 02-01-2017 at 7:00 am
Categories: EDA, Events, Intel, Samsung Foundry, Synopsys, TSMC

SPIE is the premier event for lithography held in Silicon Valley and again Scotten Jones and I will be attending. EUV is generally the star of the show and this year will be no different now that TSMC has committed to EUV production in 2019.

Last year at SPIE, TSMC presented the history of EUV development from the beginning in 1985 as … Read More

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Four Steps for Logic Synthesis in FPGA Designs

Four Steps for Logic Synthesis in FPGA Designs
by Daniel Payne on 01-30-2017 at 12:00 pm
Categories: EDA, FPGA, Synopsys

I remember meeting Ken McElvain at Silicon Compilers for the first time back in the 1980’s, he was a gifted EDA tool developer that did a lot of coding including logic synthesis, a cycle-based simulator and ATPG. Mentor Graphics acquired Silicon Compilers with Ken included, and he continued to create another logic synthesis… Read More

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Building a Virtual Prototype

Building a Virtual Prototype
by Bernard Murphy on 12-20-2016 at 7:00 am
Categories: EDA, Synopsys

I wrote recently about how virtual prototypes (in the form of VDKs) can help embedded software teams practice continuous integration. Synopsys has just released a white paper detailing a practical approach to building a VDK, using the Juno ARM development platform (ADP) to illustrate. Just as a reminder, the point of a virtual… Read More

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Nvidia Drives into New Market with Deep Learning and the Drive PX 2

Nvidia Drives into New Market with Deep Learning and the Drive PX 2
by Tom Simon on 12-03-2016 at 7:00 am
Categories: Automotive, EDA, Synopsys

Nvidia has found that video games are the perfect metaphor for autonomous driving. To understand why this is so relevant you have to realize that the way self-driving cars see the world is through a virtual world created in real time inside the processors used for autonomous driving – very much like a video game. It’s a little bit like… Read More

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ATPG, Automotive and 7nm FinFET

ATPG, Automotive and 7nm FinFET
by Daniel Payne on 11-22-2016 at 4:00 pm
Categories: Automotive, EDA, FinFET, Synopsys

The state of Texas hosted two or our industry’s big technical conferences and trade shows this year: DAC and ITC (International Test Conference). IC designers know about DAC in Austin, and test engineers know about ITC in Dallas. I travelled to Austin to cover DAC this past summer, and I was able to connect with Robert Ruiz … Read More

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Embedded Agility

Embedded Agility
by Bernard Murphy on 11-21-2016 at 12:00 pm
Categories: Automotive, EDA, Synopsys

A familiar refrain in software development, as much as in hardware development, is that the size and complexity of projects continues to grow as schedules shrink and expectations of quality can increase dramatically. A common approach to managing this challenge in software programs is agile development practices and one aspect… Read More

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Ford Motors Discusses Future Mobility Trends at Synopsys Seminar

Ford Motors Discusses Future Mobility Trends at Synopsys Seminar
by Tom Simon on 11-17-2016 at 4:00 pm
Categories: Automotive, EDA, Synopsys

Five or ten years ago it would have been hard to imagine someone from Ford Motors giving the keynote at a technology summit at a major EDA company like Synopsys. However, on November 2[SUP]nd[/SUP], Synopsys hosted a seminar on the topic of Automotive Architecture Design and System Testing, and Ford Technical Fellow Jim Buczkowski… Read More