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EDA

Electronic Design Automation

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AMD Goes 3D

AMD Goes 3D
by Paul McLellan on 12-13-2013 at 7:16 pm
Categories: EDA

I attended the 3D packaging conference in Burlingame this week. The most interesting presentation to me was by Bryan Black of AMD. He argued very convincingly that Moore’s Law is basically over for the PC microprocessor business and the way forward is going to be 3D. AMD are clearly working on all this.

Increased density and… Read More

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Taming The Interconnect In Real World For SoCs

Taming The Interconnect In Real World For SoCs
by Pawan Fangaria on 12-13-2013 at 1:30 pm
Categories: EDA

Interconnect plays a significant role in the semiconductor design of a SoC; if not architected and handled well, it can lead to an overdesigned SoC impacting on its power, performance and area. Since a SoC generally contains multiple IPs requiring different data paths to satisfy varying latency and performance cycles, it has … Read More

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Impact Conference: Focus on the IP Ecosystem

Impact Conference: Focus on the IP Ecosystem
by Daniel Payne on 12-11-2013 at 7:07 pm
Categories: EDA, Perforce

Jim Feldhan, President of Semico Research presented earlier this month at the Impact Conference on the topic: Focus on the IP Ecosystem. I’ve reviewed his 19 page presentation, and summarize it with:

  • End markets like smart phones and tablets are dominant
  • Growth drivers include the Internet of Things (IoT)
  • World semi forecast
… Read More
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Known Unknowns and Unknown Unknowns

Known Unknowns and Unknown Unknowns
by Paul McLellan on 12-11-2013 at 3:18 pm
Categories: EDA, Synopsys

Donald Rumsfeld categorized what we knew into known unknowns and unknown unknowns. In a chip design, those unknown unknowns can bite you and leave you with a non-functional design, perhaps even intermittent failures which can be among the hardest problems to debug.

Chips are too big to do any sort of full gate-level simulation,… Read More

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Designing a DDR3 System to Meet Timing

Designing a DDR3 System to Meet Timing
by Daniel Payne on 12-11-2013 at 12:00 pm
Categories: EDA, Synopsys

My very first thought when hearing about HSPICE is using it for IC simulation at the transistor-level, however it can also be used to simulate a package or PCB interconnect very accurately, like in the PCB layout of a DDR3 system where timing is critical. I attended a webinar this morning that was jointly presented by Zuken and Synopsys… Read More

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Cadence CEO Keynotes DVCON 2014!

Cadence CEO Keynotes DVCON 2014!
by Daniel Nenni on 12-10-2013 at 8:00 pm
Categories: Cadence, EDA


Next year’s DVCon attendees can expect to learn about both practical solutions to their pressing problems that can be applied today and also receive a preview of the technologies that will affect them in the near future. DVCON is March 3-6, 2014 @ the DoubleTree Hotel in San Jose.

KEYNOTE: An Executive View of Trends and Technologies… Read More

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Capturing Analog Design Intent with Verification

Capturing Analog Design Intent with Verification
by Daniel Payne on 12-08-2013 at 10:05 am
Categories: EDA, Siemens EDA

Analog IC designers are gradually adopting what digital IC designers have been doing for years, metric driven verification. When you talk with analog designers about their methodology and approach, you hear terms like artisan being used which implies mostly a manually-oriented methodology. Thanks to automation from EDA companies,… Read More

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How to Assure Quality of Power and SI Verification?

How to Assure Quality of Power and SI Verification?
by Pawan Fangaria on 12-08-2013 at 10:05 am
Categories: Ansys, Inc., EDA

As power has become one of the most important criteria in semiconductor design today, I was wondering whether there is a standard set for the power verification for an overall chip. We do have formats evolved like CPF and UPF and there are tools available to check power and signal integrity (SI), however I don’t see a standard objective… Read More

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Virtual Prototypes Made Easier for SoC Design

Virtual Prototypes Made Easier for SoC Design
by Daniel Payne on 12-06-2013 at 6:24 pm
Categories: EDA

Using a virtual prototype for your SoC design is accepted, conventional wisdom today because it can save development time by eliminating design iterations and avoid costly bugs that will cause an expensive product recall. In order to simulate your virtual prototype you need models, so a major question has always been, “Where… Read More

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Physically Aware Synthesis

Physically Aware Synthesis
by Paul McLellan on 12-06-2013 at 2:47 pm
Categories: Cadence, EDA

Yesterday Cadence had their annual front-end summit, the theme of which was physically aware design. I was especially interested in the first couple of presentations about physically aware synthesis. I joined Cadence in 1999 when they acquired Ambit Design Systems. One of the products that we had in development was called PKS… Read More