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EDA

Electronic Design Automation

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Innovation + Thoughtful Management = Productive Expansion

Innovation + Thoughtful Management = Productive Expansion
by Pawan Fangaria on 08-22-2013 at 12:00 pm
Categories: EDA

After looking at various aspects of this company, to sum up, I couldn’t find any better statement than this; thoughtful management here is actually leadership with passion which achieves tangible results. This reflects in the methodology of doing things in this company which has given it a place among top EDA companies in a span… Read More

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Web-based Circuit Design and Analysis

Web-based Circuit Design and Analysis
by Daniel Payne on 08-21-2013 at 11:27 am
Categories: EDA

Last month I blogged about CircuitLaband received some two dozen comments, so clearly there is keen interest in using web-based tools for electronic circuit design and using the cloud to save designs plus run simulations. Today I’m reporting on TINACloud, provided by a company called DesignSoft. … Read More

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Who is One Step Above Colgate and One Below P&G?

Who is One Step Above Colgate and One Below P&G?
by Paul McLellan on 08-21-2013 at 1:13 am
Categories: Dassault Systemes, EDA

So who do you think is #31 on the list on Forbes list of the most innovative companies in the world? One place above Colgate and one place below Procter and Gamble. Your first thought is probably why am I asking this on a blog covering semiconductors and going on about toothpaste manufacturers. The answer is Dassault Systèmes. Perhaps… Read More

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Test, The Forgotten Step-Child of Semiconductor Design

Test, The Forgotten Step-Child of Semiconductor Design
by Paul McLellan on 08-20-2013 at 7:56 pm
Categories: EDA, Siemens EDA

Somehow, when designing a chip it is synthesis and place & route that gets all the attention. But it is no good taping out perfect layout without also having away to test the silicon. Somehow, test just isn’t as glamorous.

On September 10-12th is the International Test Conference which, as usual, is at the Disneyland Hotel… Read More

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More to the story than bigger FPGA-based prototyping

More to the story than bigger FPGA-based prototyping
by Don Dingee on 08-19-2013 at 5:00 pm
Categories: EDA, FPGA, Synopsys

Still not convinced on the value of FPGA-based prototyping systems, or using older technology? I’ve been trying to find the story beyond just bigger, badder FPGAs in a box that you pour RTL into – and found some hints in a webinar on the Synopsys HAPS-70 from earlier this year.… Read More

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Atrenta Seminars in Asia – Making RTL Signoff Real

Atrenta Seminars in Asia – Making RTL Signoff Real
by Daniel Nenni on 08-18-2013 at 8:10 pm
Categories: EDA

Engaging with the semiconductor ecosystem is critical to surviving in the fast paced times we work in. Face to face interaction at all levels is key and semiconductor IP is a prime example. How do you ensure that your IP meets objective quality requirements before integration into your SoC, and that your SoC is ready for handoff to… Read More

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Why Adopt Hierarchical Test for SoC Designs

Why Adopt Hierarchical Test for SoC Designs
by Daniel Payne on 08-15-2013 at 4:37 pm
Categories: EDA, Synopsys, TSMC

IC designers have been creating with hierarchy for years to better manage large design sizes, however for the test world the concept of hierarchy and emerging standards is a bit newer. TSMC and Synopsys jointly created a webinarthat addresses hierarchical test, so I’ve attended it this week and summarized my findings here.… Read More

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Accelerating SoC Simulation Times

Accelerating SoC Simulation Times
by Daniel Payne on 08-15-2013 at 2:43 pm
Categories: Aldec, EDA, FPGA

There never seems to be enough time in a SoC project to simulate all of the cycles and tests that you want to run, so any technique to accelerate each run is welcomed. You can just wait for your software-based RTL simulator to finish running, or you can consider using a hardware-based accelerator approach. I learned more about one such… Read More

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Don’t Shoot Yourself in the Foot With Timing Exceptions

Don’t Shoot Yourself in the Foot With Timing Exceptions
by Paul McLellan on 08-15-2013 at 1:42 pm
Categories: EDA

Timing exceptions are ways of guiding design tools, primarily synthesis and static timing analysis (STA), but these days also place & route and perhaps other tools. Most paths in a design go from one register to the next register. Both registers are on the same clock, and the design needs to ensure that the signal can make it from… Read More

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Let’s Drive To Dearborn on 19th Sep….

Let’s Drive To Dearborn on 19th Sep….
by Pawan Fangaria on 08-15-2013 at 11:00 am
Categories: EDA, Siemens EDA


[The VLC developed by Edison2, winner of the Progressive Automotive X-Prize]

Now that we have “The Very Light Car” of the world at more than 100 MPG!! Yes, this is the car developed by Edison2, one among the three winners of the Progressive Insurance Automotive X-Prize, a global competition; Edison2 won in the main stream class. … Read More