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Calibre Update at DAC

Calibre Update at DAC
by Daniel Payne on 06-13-2013 at 12:51 pm

Mentor Graphics throws a very nice dinner party at DAC each year for journalists, bloggers and top customers, so this year I spoke with Michael Buehler-Garcia about what’s new with Calibre.

Michael Buehler-Garcia, Mentor Graphics

Our dinner venue


Q: Are there any new Calibre announcements at DAC this year?
A: No, there’s not really a new product announcement however at the October TSMC OIP you can look forward to an announcement.

Q: What’s new in the past year with Calibre?
A: We have new use models and optimization in Calibre.
20nm best practices with TSMC
– New 5GB per CPU required to get DRC runs with high check counts.
– DPT flavors: Colorless from TSMC, colored IBM-GF-Samsung. Support both flows. P&R, verification, extraction, DFM.

Q: What challenges are you seeing this year?
A: The biggest chips tend to stress the EDA flow. Run times can be days long.

Broadcom – 5.7billion transistor chip stresses the tools, so they need upgrading. EDA companies need to be involved very earlier.

Q: What improvements have there been in Calibre?
A: 3X speed ups and 2X less RAM since optimizing with TSMC at 20nm.

14nm and Samsung up to 50% run time reductions to optimize TAT.

Q: What are some of the trends that you see?
A: Opsis – U of Delaware, like MOSIS for silicon photonics. Putting a flow together with Pyxis and Opsis, adding DRC, LVS, LFD. Calibre is equation based, so can be extended to photonics. Users of Opsis can use servers at Opsis for their MPW projects.

Q: Why did Mentor build a new data center in Wilsonville?
A: The Data Center is for Internal MGC engineering, but not Calibre because they have different compute requirements. 14,000 CPUs just for Calibre uses. Talked to Google about data centers, but they really don’t use floating point. Calibre scales well, so a great stress test for data centers.

Q: How does Calibre compete with iPVS from Cadence?
A: iPVS versus RealTime, Calibre wins every time.

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