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EDA

Electronic Design Automation

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Semiconductor IP Library QA Just Got Easier

Semiconductor IP Library QA Just Got Easier
by Daniel Payne on 10-17-2013 at 12:05 pm
Categories: EDA, Fractal Technologies

Imagine that you’re working in a CAD group and just received a new library of a few hundred IP blocks and you needed to know if these blocks conform to your design and quality standards. There are many questions about library and IP quality:

  • Are all of the views consistent (layout, schematic, HDL, test, timing, SPICE)?
  • Are there
… Read More
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How to Simplify Complexities in Power Verification?

How to Simplify Complexities in Power Verification?
by Pawan Fangaria on 10-17-2013 at 11:00 am
Categories: EDA, Siemens EDA

With multiple functionalities added into a single chip, be it a SoC or an ASIC, maintaining low power consumption has become critical for any design. Various techniques at the technology as well as design level are employed to accomplish the low power target. These include thinner oxides in transistors, different sections of … Read More

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Using HLS to Turbocharge Verification

Using HLS to Turbocharge Verification
by Paul McLellan on 10-16-2013 at 8:23 am
Categories: EDA

One of the benefits of using high-level synthesis is obviously the ease of writing some algorithms in SystemC since it is at a higher level than RTL (that’s why we call it high-level synthesis!). But a second benefit is at the verification level. Since a lot of the verification gets done at the SystemC level, less needs to be done at … Read More

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Assertions verifying blocks to systems at Broadcom

Assertions verifying blocks to systems at Broadcom
by Don Dingee on 10-15-2013 at 6:00 pm
Categories: EDA, Siemens EDA

Speaking from experience, it is very difficult to get an OEM customer to talk about how they actually use standards and vendor products. A new white paper co-authored by Broadcom lends insight into how a variety of technologies combine in a flow from IP block simulation verification with assertions to complete SoC emulation with… Read More

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An ASIC Design Flow at LSI

An ASIC Design Flow at LSI
by Daniel Payne on 10-15-2013 at 1:11 pm
Categories: EDA, Synopsys

Harish Aepalais part of the Design Closure Methodology group at LSIand he recently talked about his ASIC handoff experience in a webinar. Harish works with logic and physical synthesis, timing constraints, RTL analysis and formal verification.

One challenge with ASIC handoff has been getting through design closure with the… Read More

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Layout-based ESD Checking Methodology at Nvidia

Layout-based ESD Checking Methodology at Nvidia
by Daniel Payne on 10-14-2013 at 12:43 pm
Categories: Ansys, Inc., EDA

The company Nvidiais synonymous with designing all things video and GPU, so I watched Ting Ku, director of engineering at an archived webinar today talk about: Comprehensive Layout-based ESD Check Methodology with Fast Full-chip Static and Macro-level Dynamic Solutions.… Read More

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Device Noise Analysis of Switched-Capacitor Circuits Webinar

Device Noise Analysis of Switched-Capacitor Circuits Webinar
by Daniel Nenni on 10-13-2013 at 9:00 pm
Categories: EDA


Switched-capacitor (SC) circuits are ubiquitous in CMOS mixed-signal ICs. Thermal noise, introduced by MOS switches and active amplifier circuitry, is the major performance limiter in these circuits. This webinar reviews analysis techniques to accurately analyze the noise performance of switched-capacitor circuits … Read More

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Mentor Graphics Continues To Perform Well

Mentor Graphics Continues To Perform Well
by Ashraf Eassa on 10-13-2013 at 2:00 pm
Categories: EDA, Siemens EDA

The EDA tool space has been booming in this new “mobile era” of computing. As the world transitions to system-on-chip design methodologies, and as more teams are developing even more products for an ever-broadening set of end markets, the demand for ever more sophisticated design tools has only continued to skyrocket.… Read More

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Driving Innovation in Image Sensors and High Speed AMS Design!

Driving Innovation in Image Sensors and High Speed AMS Design!
by Daniel Nenni on 10-13-2013 at 7:00 am
Categories: EDA, Tanner EDA


This is a live Silicon Valley event and yes there is such a thing as a free lunch. This is the first in a series of live SemiWiki collaborative events. I strongly believe that, especially in the age of social media, real world experience is key to the collaboration required to be successful in modern day semiconductor design. This is… Read More

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A Brief History of Tangent Systems

A Brief History of Tangent Systems
by Daniel Nenni on 10-12-2013 at 3:30 pm
Categories: EDA

In the spring of 1984, Mark Flomenhoft, Ph.D., approached Aki Fujimura, Randy Smith, and Steve Teig, to join him in developing a business plan to create a new EDA place and route (P&R) company. The three young software engineers all worked at Trilogy Systems Corporation where Mark was a director in the design automation department.… Read More