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Virtual Prototypes Made Easier for SoC Design

Virtual Prototypes Made Easier for SoC Design
by Daniel Payne on 12-06-2013 at 6:24 pm

Using a virtual prototype for your SoC design is accepted, conventional wisdom today because it can save development time by eliminating design iterations and avoid costly bugs that will cause an expensive product recall. In order to simulate your virtual prototype you need models, so a major question has always been, “Where do I get all these models for each block in my SoC, many of which are IP purchased through multiple vendors?”

Carbon Design Systems provides both a virtual platform plus models to enable virtual prototyping, and they have just extended their agreement with Cadence Design System who supplies a popular DDR3 memory controller. Read the press release here.

Simulating a Virtual Prototype with Carbon SoC Designer Plus

I wanted more details than the press release provided, so I followed up with Bill Neifert of Carbon Design:

Bill Neifert, CTO at Carbon Design Systems


Q: Why is this announcement important and to whom?
A: Accurate virtual prototypes are a vital part of the development process for leading edge SoCs. This partnership enables customers developing these SoCs to more easily design with and optimize designs using Cadence IP. By including Cadence IP in Carbon’s next generation of CPAKs, it will enable designers to get up and running quickly and leverage the value of Cadence expanding IP library earlier in the design cycle.

Q: When did the partnership first begin with Cadence? What is the history?
A: This agreement originally started as a partnership with Denali for their DDR3 memory controllers in April of 2010. We successfully deployed multiple 100% accurate memory controller models to mutual customers and prospects through the years. After Denali’s purchase by Cadence we’ve amended the agreement a few times to add additional pieces of IP such as the Gigabit Ethernet MAC and PCI Express controller.

Q: Are the Carbon models of the Cadence DDR3 memory controller the first new models under this agreement?
A: These models and accompany Carbon Performance Analysis Kits (CPAKs) have been available since April 2010. We’ll be rolling out models of the rest of the Cadence IP portfolio in the upcoming month or two.

Q: How many design IP models does Cadence have that will be available on your portal? Is there a list that I can see?
A: We will have models of all of Cadence’s IP available on the portal, Cadence’s IP library is available here and contains:

  • Memory Design IP
  • Storage Design IP
  • Connectivity Design IP
  • Analog Design IP
  • Core SoC Building Blocks

Q: What are the new CPAKs coming out, and when?
A: The new CPAKs will be rolled out based upon customer interest. We typically do this by modifying an existing CPAK to incorporate a new piece of IP or replace an existing one so this process is pretty straightforward

Q: Does this partnership change anything with Tensilica processors?
A: Carbon has a longstanding partnership with Tensilica which is unchanged with this agreement

Q: Which web site should customers go to, Cadence or Carbon or either? Why?
A: All of the models will be exclusively available from Carbon’s IP Exchange web portal: This web site is already the industry’s only source for accurate models of IP from other leading IP vendors such as ARM and Imagination Technologies so it’s a natural place.

Q: Which customers benefit from this partnership?
A: Customers performing IP selection, configuration, performance analysis and pre-silicon firmware development

More Articles by Daniel Payne …..

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