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EDPS Monterey. Agenda Now Available

EDPS Monterey. Agenda Now Available
by Paul McLellan on 03-12-2013 at 8:13 pm

For 20 years there has been the Electronic Design Process Symposium. It has been held each April and for the last few years at least has always been in Monterey at the Monterey Beach Resort. This year it is Thursday and Friday April 18th/19th.

The keynote on the first day is by Ivo Bolsens of Xilinx on The All-programmable SoC —Read More


RTDA at Altera

RTDA at Altera
by Paul McLellan on 03-12-2013 at 8:05 pm

I talked to Yaron Kretchmer of Altera to find out how they are using RTDA’s products. I believe that Altera are the oldest customer of RTDA, dating back over 15 years, originally used by the operations team around the test floor before propagating out in the EDA and software worlds more recently.

Altera use two RTDA tools, LicenceMonitorRead More


Virtual Platforms, Acceleration, Emulation, FPGA Prototypes, Chips

Virtual Platforms, Acceleration, Emulation, FPGA Prototypes, Chips
by Paul McLellan on 03-12-2013 at 7:13 pm

At CDNLive today Frank Schirrmeister presented a nice overview of Cadence’s verification capabilities. The problem with verification is that you can’t have everything you want. What you really want is very fast runtimes, very accurate fidelity to the hardware and everything available very early in the design … Read More


Visually Debugging IC Designs for AMS and Mixed-Languages

Visually Debugging IC Designs for AMS and Mixed-Languages
by Daniel Payne on 03-12-2013 at 4:18 pm

With an HDL-based design methodology many IC engineers code in text languages like SystemVerilog and VHDL, so it’s only natural to use a text-based debug methodology. The expression that, “A picture is worth a thousand words” comes to my mind and in this case a visual debug approach is worth considering for … Read More


Cadence To Acquire Tensilica

Cadence To Acquire Tensilica
by Paul McLellan on 03-11-2013 at 5:54 pm

You have probably already seen the news: Cadence is acquiring Tensilica for $380M. Cadence has been relatively late to the IP party compared to Synopsys. In contrast, Mentor was early, got into the IP business before it was really profitable and ended up shutting down the business.

Tensilica is quite sizable. It has over 200 licensees,… Read More


Sanjiv Kaul: Is HLS About to Take Off?

Sanjiv Kaul: Is HLS About to Take Off?
by Paul McLellan on 03-10-2013 at 8:10 pm


At the end of last week I talked to Sanjiv Kaul, the new CEO of Calypto. Just to give a little background for those that haven’t been following along at home, Calypto was founded to try and solve the very hard problem of sequential logical equivalence checking (mostly by people from the engineering team that I managed at Ambit).… Read More


We are Live at CDNLive 2013!

We are Live at CDNLive 2013!
by Daniel Nenni on 03-10-2013 at 7:00 pm

Dr. Paul McLellan and I will be covering CDNLive this week, one of the premier EDA events of the year. Take a look at the agenda and exhibits, this year it looks like a full on Design Automation Conference! There is definitely something for everyone!

Get ready for two full days of content with more than a hundred tracks and keynotes by… Read More


Reliability is the New Power

Reliability is the New Power
by Paul McLellan on 03-09-2013 at 9:56 am

It has be come a cliche to say that “power is the new timing”, the thing that keeps designers up at night and drives the major architectural decisions in big SoCs. Nobody is saying it yet but perhaps “reliability is the new power” will be tomorrow’s received wisdom.

I talked to Adrian Evans of IROCTech… Read More


Tanner EDA v16 OpenAccess is here!

Tanner EDA v16 OpenAccess is here!
by Daniel Nenni on 03-07-2013 at 4:00 pm

Tanner EDA is a pleasure to work with, they are big on collaboration and customers absolutely love their tools. With the Synopsys acquisition of SpringSoft, Tanner needs to step up and fill the void of the affordable Laker tools. Take a close look at their new v16 release and let me know how they are doing.

New capabilities for back-endRead More


Multiprotocol 10G-KR and PCIe Gen-3 PHY IP will support big data and smartphone explosion

Multiprotocol 10G-KR and PCIe Gen-3 PHY IP will support big data and smartphone explosion
by Eric Esteve on 03-07-2013 at 7:47 am

We have frequently said in Semiwiki how crucial is it for the SC industry to benefit from high quality PHY IP… even if, from a pure business point of view (MBA minded), PHY IP business does not look so attractive. In fact, to be able to design on-the-edge SerDes and PLL (the two key pieces), you need to build and maintain a highly skilled… Read More