hip webinar automating integration workflow 800x100 (1)
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EDA

Electronic Design Automation

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Hot Topic – CMOS Image Sensor Verification!

Hot Topic – CMOS Image Sensor Verification!
by Daniel Nenni on 04-29-2013 at 7:30 pm
Categories: EDA

Mobile applications require CMOS image sensor devices that have a low signal-to-noise ratio (SNR), low power, small area, high resolution, high dynamic range, and high frame rate. CMOS image sensor imaging performance is noise limited requiring accurate noise analysis on the pixel array electronics and column readout circuitry.… Read More

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Beyond one FPGA comfort zone

Beyond one FPGA comfort zone
by Don Dingee on 04-29-2013 at 5:00 pm
Categories: Aldec, EDA, FPGA

Unless you are a small company with one design team, the chance you have standardized on one FPGA vendor for all your needs, forever and ever, is unlikely. No doubt you probably have a favorite, because of the specific class of part you use most often or the tool you are most familiar with, but I’d bet you use more than one FPGA vendor routinely.… Read More

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Transient Noise Analysis (TNA)

Transient Noise Analysis (TNA)
by Rupindermand on 04-29-2013 at 4:21 pm
Categories: EDA, Tanner EDA

Tanner EDA Applications Engineers see a broad range of technical challenges that our users are trying to overcome. Here’s one worth sharing – it deals with transient noise analysis (TNA) for a comparator design. The customer is a producer of advanced flow measurement devices for application in medicine and research. The designer… Read More

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Challenges of 20nm IC Design

Challenges of 20nm IC Design
by Daniel Payne on 04-29-2013 at 11:38 am
Categories: EDA, Synopsys

Designing at the 20nm node is harder than at 28nm, mostly because of the lithography and process variability challenges that in turn require changes to EDA tools and mask making. The attraction of 20nm design is realizing SoCs with 20 billion transistors. Saleem Haider from Synopsys spoke with me last week to review how Synopsys… Read More

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Properly Handing Of Clock Tree Synthesis Specifications

Properly Handing Of Clock Tree Synthesis Specifications
by Randy Smith on 04-28-2013 at 1:00 pm
Categories: EDA

Given today’s design requirements with respect to low power, there is increasing focus on the contribution to total power made by a design’s clock trees. The design decisions made by the front-end team to achieve high performance without wasting power must be conveyed to back-end team. This hand-off must be accurate… Read More

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Reduce Errors in Multi-threaded Designs

Reduce Errors in Multi-threaded Designs
by Randy Smith on 04-28-2013 at 1:00 pm
Categories: EDA

Many advanced algorithmic IPs are described in C++. We use this language because of its flexibility. Of course software algorithms are written to be executed on processors so they don’t solve all the issues of getting the algorithm implemented in hardware directly. This is not simply a high-level synthesis (HLS) issue. Usually… Read More

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Using Virtual Platforms to Make IP Decisions

Using Virtual Platforms to Make IP Decisions
by Paul McLellan on 04-27-2013 at 10:48 am
Categories: Arm, EDA, IP

Most SoC designs these days consist largely, but not entirely, of purchased IP blocks. But there are lots of tradeoffs involved in selecting IP blocks, and since those tradeoffs change with process node, even decisions that seem “obvious” based on the last generation of the design, may not be so clear cut. Even if you… Read More

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TSMC ♥ Solido

TSMC ♥ Solido
by Daniel Nenni on 04-27-2013 at 8:00 am
Categories: EDA, Foundries, Solido, TSMC

Process variation has been a top trending term since SemiWiki began as a result of the articles, wikis, and white papers posted on the Solido landing page. Last year Solido and TSMC did a webinar together, an article in EETimes, and Solido released a book on the subject. Process variation is a challenge today at 28nm and it gets worse… Read More

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Mentor CEO Wally Rhines U2U Keynote

Mentor CEO Wally Rhines U2U Keynote
by Daniel Nenni on 04-26-2013 at 2:00 pm
Categories: EDA, Siemens EDA

You will never meet a more approachable CEO in the semiconductor ecosystem than Dr. Walden C. Rhines. The first time I met Wally was way back when I blogged for food and he invited me over for lunch. Even better, a year or two later I was having dinner with a friend at the DBL Tree in San Jose. Wally was waiting for his flight home so he joined… Read More

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When installing a sink, it’s a lot faster to buy a saw

When installing a sink, it’s a lot faster to buy a saw
by Don Dingee on 04-25-2013 at 8:10 pm
Categories: EDA, Siemens EDA

Mentor’s announcement from Design West this week pretty much signals the end of standalone ESL tools, in favor of more useful stuff. They have pulled the pieces of their Sourcery CodeBench environment along with their embedded Linux offering and their Vista virtual prototyping platform into a native embedded software development… Read More