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Mentor Seminar: Evolution of diagnosis-driven yield analysis

Mentor Seminar: Evolution of diagnosis-driven yield analysis
by Beth Martin on 10-08-2013 at 1:20 pm

It’s a fact that new process nodes come with some amount of yield challenges. One way to find and eliminate silicon defects is through diagnosis-driven yield analysis (DDYA), which is the topic of a free seminar by Mentor Graphics in Fremont this Thursday, October 10 from 11:30am – 2pm (yes, lunch is included because Mentor… Read More


Atrenta Japan Technoloogy Forum

Atrenta Japan Technoloogy Forum
by Paul McLellan on 10-08-2013 at 12:27 am

As they have done for the last few years, Atrenta held its fifth annual user group meeting at the Shin Yokohama Kokusai Hotel on September 13. The attendees are a mixture of customers and other interested members of the semiconductor supply chain. There were nearly 90 people there representing 48 different companies in Japan.

The… Read More


Cadence’s System-to-Silicon Verification Summit

Cadence’s System-to-Silicon Verification Summit
by Randy Smith on 10-06-2013 at 6:00 pm

At this year’s DAC, I spoke with several friends at Cadence. I got the distinct impression that something at Cadence had changed. There was a sense of pride and accomplishment that it seems to me had drifted away over the years. Now employees were speaking with true conviction about the accomplishments of the product development… Read More


A Big Thank You to EDA and IP

A Big Thank You to EDA and IP
by Daniel Nenni on 10-05-2013 at 10:00 pm

Electronic Design Automation Software and Semiconductor Intellectual Property are not so much the tail that wags the dog, rather they are like the heart of an elephant, tiny in comparison but without which there is no elephant. There is no doubt that EDA and IP have been key enablers of the semiconductor industry for the past 50 years… Read More


Synopsys: Getting To Know EDA’s Heavyweight Champion

Synopsys: Getting To Know EDA’s Heavyweight Champion
by Ashraf Eassa on 10-05-2013 at 8:00 pm

From chip IP vendor ARM Holdings to semiconductor foundry Taiwan Semiconductor, there have been many winners from the mobile device revolution that was sparked by Apple’s introduction of the iPhone. However, while these big-ticket names get all the fame and glory, the electronic design automation space (“EDA” for short) is … Read More


High resolution Analog CMOS IC Design

High resolution Analog CMOS IC Design
by Daniel Payne on 10-04-2013 at 5:02 pm

My background includes transistor-level IC design, so I take delight in talking with engineers like Dr. Lanny Lewyn that are still practicing the art and science of analog IC design. Dr. Lewynis a Life Senior Member of the IEEE and has a consulting business. If you live in Santa Clara, then consider attending a live seminar on OctoberRead More


Computer History Museum Party!

Computer History Museum Party!
by Daniel Nenni on 10-04-2013 at 3:00 pm

More details are now available for the EDA 50[SUP]th[/SUP] anniversary event on October 16[SUP]th[/SUP]. If you have not been to the museum lately this is a must see event as it is all new. Definitely check out the auction items! Just do not bid against me or it will get very expensive for one of us. I’m watching Storage Wars reruns so… Read More


Cadence Grows VIP Business – What’s New?

Cadence Grows VIP Business – What’s New?
by Pawan Fangaria on 10-04-2013 at 10:00 am

VIPs (Verification IPs) are really important in this complex world of SoCs which involve various IPs, interfaces and continuously evolving protocols and standards, thus making the task of verifying an overall system extremely challenging. And the verification must be done in minimum possible run-time and memory consumption.… Read More


High-Sigma Standard Cell Optimization!

High-Sigma Standard Cell Optimization!
by Daniel Nenni on 10-03-2013 at 11:00 am

Standard cell optimization is an important problem, because the speed, power, and area of cells has a direct impact speed, power, and area of the whole chip. Typically, standard cell optimization been done with simple in-house local-optimizer scripts. However, these optimizers have had several flaws: they don’t properly capture… Read More


A Mixed-Signal IC Summit in San Jose

A Mixed-Signal IC Summit in San Jose
by Daniel Payne on 10-03-2013 at 9:26 am

Analog and mixed-signal ICs are tougher to design and verify compared to digital, so if you want to learn more about best practices from actual AMS engineers then consider attending a summitthat is sponsored by Cadence Design Systems next Thursday, October 10th in San Jose from 8:00AM until 6:30PM.

They’ve lined up an interesting… Read More