As we have moved towards lower process nodes to improve performance of ICs with higher density and functionality, many manufacturing effects have appeared which can render ICs useless, even though the layout design could be correct as per traditional design rules. What is more worrisome is the variability of these effects which… Read More
Electronic Design Automation
RTL Power Optimization
More so than most aspects of design, power reduction suffers from a paradox that early in the design cycle when the gains are the largest, the accuracy of power estimation is the lowest, and then late in the design cycle, when everything is known pretty much exactly it is too late to make anything other than trivial optimizations. … Read More
SoC Power Integrity Challenges
At DAC in 2012 I visited a few dozen EDA companies and blogged 32 articles, however I didn’t get to see what Apache Design (now a subsidiary of ANSYS) had to say. I did have 20 minutes today to watch their latest video on SoC Power Integrity Challenges and decided to share what I learned. If you want to watch the video at Tech Online,… Read More
Cutting the Key to 14nm Lithography
It appears that immersion lithography is now the plan of record for manufacturing ICs at 14nm. How is it possible to use 193nm wavelength light at 14nm? How can we provide the process window to pattern the such tight pitches? The secret lies in computational lithography. For 20nm, the two key innovations in computational lithography… Read More
PCI Express IP vendor Cascade acquisition by Synopsys…
… is now 8 years old, and the money paid for this 10 engineers start-up was considered, at that time, as a “bingo” for Cascade’s funders: “In October 2004, the Company completed the acquisition of Cascade Semiconductor Solutions, Inc. (Cascade) for total upfront consideration of $15.8 million and contingent consideration of … Read More
IC Test Debug at Altera
My background is IC design engineering, so it’s always a delight to talk with another engineer on their chip challenges. Today I spoke by phone with Sucharita Biswas, a Senior Hardware Engineer at Altera involved in IC test debug for FPGA devices.
Mentor Graphics User2User Conference
April 25, 2013, San Jose, CA
Click here to register.
Come hear Mentor Graphics CEO, Wally Rhines, 2013 Kaufman Award Winner,Chenming Hu, and Xilinx Senior VP,Victor Peng, at the User2User Conference in San Jose.
KEYNOTES
Organizing by Design
9:00am – 9:50am
Walden C. Rhines | CEO & Chairman | Mentor Graphics
Winning products… Read More
For power and performance, Fins or BOXes?
I recently spoke to Arvind Narayanan, Product Marketing Manager for Mentor’s place and route division about emerging technology. This of course led to FinFETS, FDSOI, performance, power, and cost-benefit. The battle between FDSOI and FinFETs, said Narayanan, is going to be something to watch.
Both FDSOI and FinFET technologies… Read More
RTL Restructuring
Hierarchical IC design has been around since the dawn of electronics, and every SoC design today will use hierarchy for both the physical and logical descriptions. During the physical implementation of an SoC you will likely run into EDA tool limits that require a re-structure of the hierarchy. This re-partitioning will cause… Read More
Kathryn Kranen Wins UBM Lifetime Achievement Award 2013
UBM’s EETimes and EDN today announced Kathryn Kranen as the lifetime achievement award winner for this years ACE awards program. Kathryn, of course, is the CEO of Jasper (and is also currently the chairman of EDAC). Past winners exemplify the prestige and significance of the award. Since 2005 the award was given to Gordon… Read More
Weebit Nano Brings ReRAM Benefits to the Automotive Market