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Solido Patent Enabling Variation-Aware Custom IC Design

Solido Patent Enabling Variation-Aware Custom IC Design
by Daniel Nenni on 05-12-2014 at 8:00 am

 This is patent number twelve for Solido Design Automation THE leading provider of variation analysis and design software for high yield and performance IP and system-on-chip (SOCs). Additional patents are pending on high-sigma analysis, high-dimensional data mining, and other technologies to design and verify custom integrated circuits.

It has been my pleasure to work with Solido on strategic foundry relationships and other business development tasks for close to five years now. Solido’s product, Variation Designer, is used by top semiconductor companies to boost SPICE simulator efficiency by dramatically reducing number of simulations for PVT, 3- to high-sigma Monte Carlo and variation debug while increasing design coverage.

If you want to know who Solido’s customers are think SoC companies and just about everyone else who cares about yield at 40nm and below. In fact, you will be hard pressed to find a fabless company with an SRAM team that does NOT use Solido for high-sigma verification.


  • Method and system for verification of electrical circuit designs at process, voltage, and temperature corners. Enables users to signoff designs under PVT variation, reducing the simulations by 2-10X+ compared to brute-force simulation of all corners. U.S. Patent No. 8,612,908.
  • Monte Carlo-based accurate corner extraction. Designers can extract 3-sigma statistical PVT corners on circuit outputs with a minimal number of simulations, even for circuits with 100K+ devices. U.S. Patent No. 8,494,670.
  • Interactive schematic for use in analog, mixed-signal, and custom digital circuit design. Users are able to to quickly identify variation hotspots on schematics themselves. U.S. Patent No. 7,761,834.
  • Pruning-based variation-aware design. Enables designers to perform variation-aware design in a unified flow, where corners are the centerpiece. U.S. Patent No. 8,074,189.
  • Model building optimization. Designers can further reduce the number of SPICE simulations inside several Solido Variation Designer applications including Fast Monte Carlo and Cell Optimizer. U.S. Patent No. 8,006,220.
  • On-the-fly improvement of certainty of statistical estimates in statistical design, with corresponding visual feedback. During a run of Solido Variation Designer, designers can quickly assess the statistical confidence of yield & output predictions, how uncertainty reduces over time, with real-time updates. U.S. Patent No. 8,589,138.
  • Global statistical optimization, characterization, and design. Enables users to explore the space of possible circuit sizings and gain extensive insight into the relation from design variables to outputs. U.S. Patent No. 8,024,682.
  • Data-mining-based knowledge extraction and visualization of analog/mixed-signal/custom digital circuit design flow. Offers insights into the effects of variation on their circuits, and the causes of that variation, “for free” via data science technologies to mine existing SPICE simulations. U.S. Patent No. 7,707,533.
  • Modeling of systems using canonical form functions and symbolic regression. Facilitates manual equation-based analysis, by suggesting easy-to-understand equations that relate design, environmental and process variables to outputs. U.S. Patent No. 8,332,188.
  • System and method for determining and visualizing tradeoffs between yield and performance in electrical circuit designs. Enables users to rapidly explore the relationship between circuit performances and yield in a visual, interactive fashion. U.S. Patent No. 7,689,952.
  • Method and system for proximity-aware circuit design. Designers can perform electrically-aware layout design and handle well proximity and other effects, without the inconvenience of tight coupling to front-end design tools. U.S. Patent No. 8,281,270.
  • Trustworthy multi-objective structural synthesis and expert knowledge extraction with application to analog circuit design. Enables users to quickly explore thousands of possible circuit topology options, and understand the strengths and weaknesses of each topology. U.S. Patent No. 8,443,329.

    Solido Events at DAC:
    Solido DAC Booth #933 Variation Designer Demo Register
    June 2, 10:30am DAC Panel on Variation-Aware Custom Design Best Practices Register
    June 2-4, Solido TSMC Theatre presentation

    About Solido Design Automation Inc.
    Solido Design Automation Inc. provides fast, accurate variation analysis and design software for custom IC’s so that our customers can achieve maximum yield and performance in their designs. Solido’s product, Variation Designer, boosts simulator efficiency by dramatically reducing number of simulations for PVT, 3- to high-sigma Monte Carlo and variation debug while increasing design coverage. Variation Designer is being used by top semiconductor companies and is qualified by TSMC and GLOBALFOUNDRIES to design memory, standard cell, custom digital and analog/RF IC’s at leading design nodes. The privately held company is venture capital funded and has offices in California, Asia, Europe and Canada. For further information, visit www.solidodesign.com.

    More Articles by Daniel Nenni…..

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