Banner Electrical Verification The invisible bottleneck in IC design updated 1
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EDA

Electronic Design Automation

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On-Chip Clock Generation beyond Phase Locked Loop

On-Chip Clock Generation beyond Phase Locked Loop
by Daniel Nenni on 03-07-2014 at 8:00 am
Categories: EDA

Inside a today’s typical VLSI system, there are millions of electrical signals. They make the system perform what it is designed to do. Among those, the most important one is the clock signal. From an operational perspective, clock is the timekeeper of the electrical world inside the chip/system. From a structural perspective,… Read More

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How to meet 3Ps in 3D-ICs with sub-20nm Dies?

How to meet 3Ps in 3D-ICs with sub-20nm Dies?
by Pawan Fangaria on 03-06-2014 at 1:30 am
Categories: Ansys, Inc., EDA

It feels to be at the top of semiconductor technology by having dies with high density of semiconductor design at sub-20nm technology node stacked together into a 3D-IC to form a complete SoC which can accommodate billions of gates. However there are multiple factors to be looked at in order to make that successful amid often conflicting… Read More

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Calypto: the View From the Top

Calypto: the View From the Top
by Paul McLellan on 03-05-2014 at 10:37 pm
Categories: EDA

At DVCon today I talked to Sanjiv Kaul, the CEO of Calypto. Just as a reminder, Calypto have 3 products, SLEC (sequential logical equivalence checking, also called sequential formal verification), PowerPro (sequential RTL level power reduction) and Catapult High Level Synthesis (that they took over from Mentor in 2011 in a complicated… Read More

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Automating PCB Timing Closure, Saving Up to 67%

Automating PCB Timing Closure, Saving Up to 67%
by Daniel Payne on 03-05-2014 at 10:10 am
Categories: Cadence, EDA

The benefits of using EDA software is that it can automate a manual process, like PCB timing closure, saving you both time and engineering effort. This point was demonstrated today as Cadenceadded new timing-closure automation to their Allegroproduct family, calling it Allegro TimingVision. On Tuesday I spoke with Hemant Shah… Read More

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What I Didn’t Know about Electronic Design Automation

What I Didn’t Know about Electronic Design Automation
by Daniel Payne on 03-04-2014 at 7:36 pm
Categories: EDA

I started using internal EDA tools at Intel beginning in 1978 and have worked in the commercial EDA industry since 1986, so it was a delight to read a chapter about EDA in Nenni and McLellan’s newest book: Fabless – The Transformation of the Semiconductor Industry. Starting in the 1970’s the authors talk about… Read More

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Dr. Walden Rhines Vision on Semiconductor & India

Dr. Walden Rhines Vision on Semiconductor & India
by Pawan Fangaria on 03-04-2014 at 11:00 am
Categories: EDA, Siemens EDA

Last month India Electronics & Semiconductor Association (IESA) held its Vision Summit at Bangalore in which luminaries from across the semiconductor and electronics industry presented their views about the future of this industry and India’s progress. Dr. Walden C. Rhines, Chairman and CEO of Mentor Graphicspresented… Read More

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Synopsys Announces Verification Compiler

Synopsys Announces Verification Compiler
by Paul McLellan on 03-04-2014 at 8:00 am
Categories: EDA, Synopsys

Integration is often an underrated attribute of good tools, compared to raw performance and technology. But these days integration is differentiation (try telling that to your calculus teacher). Today at DVCon Synopsys announced Verification Compiler which integrates pretty much all of Synopsys’s verification technologies… Read More

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Does Multiprotocol-PHY IP really boost TTM?

Does Multiprotocol-PHY IP really boost TTM?
by Eric Esteve on 03-04-2014 at 4:33 am
Categories: IP, Synopsys

I have often written in Semiwiki about high speed PHY IP supporting Interface protocols (see for example this blog), the SoC cornerstone, almost as crucial as CPU, GPU or SDRAM Memory Controller. When you architect a SoC, you first select CPU(s) and/or GPU(s) to support the system basic functionality (Processor for Mobile application,… Read More

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Effect of Inductance on Interconnect

Effect of Inductance on Interconnect
by Daniel Nenni on 03-02-2014 at 11:00 am
Categories: EDA

In previous design generations interconnect could safely be modeled by extraction using just R and C values. Parasitics in interconnect are important because they can affect the operating frequency or phase error in circuits like VCO’s. The need to model parasitics properly in wires is just as applicable in PA’s, LNA’s and for… Read More

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Locked on FPGA design brand recognition

Locked on FPGA design brand recognition
by Don Dingee on 02-28-2014 at 3:30 pm
Categories: Aldec, EDA, FPGA, Xilinx

Back in the days where computing was dominated by a few big (and now mostly dearly departed) names, there was a saying: “Nobody ever got fired for buying IBM.” The relative safety of immediate brand recognition, especially among non-technical upper management, dissuaded many users from recommending or even seeking out other … Read More