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Do You Need to Worry About Soft Errors?

Do You Need to Worry About Soft Errors?
by Paul McLellan on 05-22-2013 at 6:51 pm

As we get down to smaller and smaller process nodes, the problem of soft errors becomes increasingly important. These soft errors are caused by neutrons from cosmic rays, alpha particles from materials used in manufacture and other sources. For chips that go into systems with high reliability this is not something that can be ignored.… Read More


IC Place and Route Perspective from Users at DAC

IC Place and Route Perspective from Users at DAC
by Daniel Payne on 05-22-2013 at 11:44 am

One of the most useful ways to learn about an EDA tool is to talk with other users that have experience with that tool. IC Place and Route tools are complex and yet necessary to implement every SoC designed today, so at DAC in just two weeks you have a chance to hear first-hand from several P&R tool users. To get a better idea about these… Read More


Layout-based ESD Check Methodology with Fast, Full-chip Static and Macro-level Dynamic

Layout-based ESD Check Methodology with Fast, Full-chip Static and Macro-level Dynamic
by Daniel Payne on 05-22-2013 at 10:25 am

Nvidia designs some of the most powerful graphics chips and systems in the world, so I’m always eager to learn more about their IC design methodology. This week I’ve had the chance to talk with Ting Ku, Director of Engineering at Nvidia about his DAC talkin the Apache booth in exactly two weeks from today. RegistrationRead More


The Only DM Platform Integrated with All Major Analog and Custom IC Design Flows

The Only DM Platform Integrated with All Major Analog and Custom IC Design Flows
by Daniel Nenni on 05-22-2013 at 10:00 am

As I have mentioned before, Cliosoft is the biggest little company in EDA with the most talked about products on SemiWiki. At DAC, ClioSoft will introduce integrated SOS design management (DM) solutions providing revision control, design management and multi-site team collaboration for Aglient Technologies’ Advanced Design… Read More


Transistor-Level Update from Cadence at DAC

Transistor-Level Update from Cadence at DAC
by Daniel Payne on 05-20-2013 at 7:47 pm

My 8 years as an IC circuit designer were at the transistor-level, so if that interests you as well then consider what there is to see from Cadence at DAC this year. IC design technology is changing quickly, so keeping up to date is important for your job security and continual education goals.

Here’s what I would recommend attending… Read More


Samsung’s Life of Pi @ Apache @ DAC

Samsung’s Life of Pi @ Apache @ DAC
by Paul McLellan on 05-20-2013 at 4:51 pm

Last week I talked to Eileen You of Samsung-SSI to get a preview on what they will be talking about at Apache’s customer theater at DAC. Their presentation is titledThe Life of PI: SoC Power Integrity from Early Estimation to Design Sign-off. The ‘PI’ stands for Power Integrity.

Samsung-SSI’s operations… Read More


Tempus: Cadence Takes On PrimeTime

Tempus: Cadence Takes On PrimeTime
by Paul McLellan on 05-20-2013 at 7:00 am

Today Cadence announced Tempus, their new timing signoff solution. This has been in development for at least a couple of years and has been built from the ground up to be massively parallelized. Not just that different corners can be run in parallel (which is basically straightforward) but that large designs can be partitioned … Read More


Design Data Management – Key Winning Strategy!

Design Data Management – Key Winning Strategy!
by Pawan Fangaria on 05-19-2013 at 9:30 pm

In a complex semiconductor market today, characterized by ever increasing design size and complexity, long design cycle, rapid technological advancement, intense competition, pricing pressure, small window of opportunity, development and cross-functional teams spread across the globe and multiple design partners including… Read More


CEO Interview: Jens Andersen of Invarian

CEO Interview: Jens Andersen of Invarian
by Daniel Nenni on 05-19-2013 at 9:10 pm

Invarian is an interesting EDA company that sees a niche market opening in the physical verification space. There are a number of converging factors driving this opportunity. Electromigration and voltage-drop for full-chip analysis demands SPICE level accuracy with fast runtimes. Invarian solves that problem with macro … Read More


Complete Schedule of Synopsys 2013 DAC Events, Panels & Paper Participation (Free Food!)

Complete Schedule of Synopsys 2013 DAC Events, Panels & Paper Participation (Free Food!)
by Daniel Nenni on 05-19-2013 at 9:01 pm

Funny story, @ #49DAC I saw Aart with a very relaxed look on his face looking at the exhibit hall and in my mind he was thinking, “Mine, all mine!” But I digress……. Synopsys is the #1 EDA company for a reason and here is the supporting data for that hypothesis:

Synopsys is committed to accelerating Innovation… Read More