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TSMC ♥ Cadence!

TSMC ♥ Cadence!
by Daniel Nenni on 10-11-2014 at 4:30 pm

One of the questions I routinely ask amongst the fabless semiconductor ecosystem is, “How are the EDA vendors doing?” There are always complaints because, let’s face it, we all like to complain. On occasion however I do hear about a vendor who goes above and beyond the call of duty and it really brightens my day.

Of late,… Read More


What’s next in test compression?

What’s next in test compression?
by Beth Martin on 10-10-2014 at 4:45 pm

If you’ll be at ITC TestWeek in Seattle (Oct 20-23), here’s one event you don’t want to miss: a technology reception hosted by Mentor, with Janusz Rajski and Nilanjan Mukherjee as the featured speakers. It is free to ITC attendees and you can register here. [If for some crazy reason you haven’t registered for ITC yet, do that… Read More


Full-Chip Electromigration Analysis

Full-Chip Electromigration Analysis
by Daniel Payne on 10-10-2014 at 7:00 am

I’ll never forget debugging my first DRAM chip at Intel, peering into a microscope and watching the aluminum interconnect actually bubble and dissolve as the voltage was increased, revealing the destructive effects of Electromigration (EM) failure. That was back in 1980 using 6 um, single level metal technology, so imagine… Read More


Maker Movement Embraced by Major Semiconductor Companies

Maker Movement Embraced by Major Semiconductor Companies
by Tom Simon on 10-09-2014 at 10:00 pm

How the Arduino Changed Embedded System Development Forever

In 2005 with the development of the Arduino, everything changed for people building things that required a microcontroller. The Arduino brought with it a low price standard, and open, hardware platform and an easy to use open source development environment. It was … Read More


StarVision to Debug and Analyze Designs at All Levels

StarVision to Debug and Analyze Designs at All Levels
by Pawan Fangaria on 10-09-2014 at 4:00 pm

In today’s SoC world where multiple analog and digital blocks along with IPs at different levels of abstractions are placed together on a single chip, debugging at all levels becomes quite difficult and clumsy. While one is working at the top level and needs to investigate a particular connection at an intermediate hierarchical… Read More


10nm, the View from IBM

10nm, the View from IBM
by Paul McLellan on 10-05-2014 at 7:01 am

On the Cadence booth at DAC, Lars Liebmann of IBM presented on the challenges of 10nm. As he put it, how the lithography folks are keeping things very interesting for the EDA tool development engineers. Although 14nm/16nm hasn’t yet ramped into HVM, the advanced work for tools and IP has all moved to 10nm. Although Lars gave… Read More


Key Collaboration to Enable Designs at Advanced Nodes

Key Collaboration to Enable Designs at Advanced Nodes
by Pawan Fangaria on 10-03-2014 at 10:00 pm

In the semiconductor ecosystem, several partners (or better to say stakeholders) join together in the overall value chain to finally output the most coveted chip, err I should say SoC these days. It becomes really interesting when we start analyzing the real value added by each of them, none appears to be less. Well, then to whom … Read More


What’s Behind Carbon System Exchange – How Will it Scale?

What’s Behind Carbon System Exchange – How Will it Scale?
by Pawan Fangaria on 10-01-2014 at 4:00 pm

Earlier this year, when I was looking at Carbon’spast year performance which provided record breaking revenue with whopping jump in bookings, one thing was certain that Carbon Performance Analysis Kits (CPAKs) would drive major growth in future, not only for Carbon, but also for the semiconductor industry. It will initiate … Read More


IP and Design Management Done Right

IP and Design Management Done Right
by Daniel Payne on 09-30-2014 at 4:30 pm

At DACin San Francisco this past June I was able to visit and blog about two dozen EDA companies, however there were so many more products and events to see that I couldn’t possibly have enough time to enjoy them all. Fortunately for me there were plenty of videos made of vendor presentations, so this week I got caught up a bit by… Read More


ANSYS Tools Shine at FinFET Nodes!

ANSYS Tools Shine at FinFET Nodes!
by Pawan Fangaria on 09-30-2014 at 4:00 pm

In the modern semiconductor ecosystem we are seeing rapid advancement in technology breaking past once perceived limits; 28nm, 20nm, 16-14nm, 10nm and we are foreseeing 7nm now. Double and multi-patterning are already being seen along with complex FinFET structures in transistors to gain the ultimate advantages in PPA from… Read More