My first experience with logic synthesis was at Silicon Compilers in the late 1980s using a tool called Genesil. Process technology since that time has moved from 3 um down to 20 nm, so there are new challenges for RTL synthesis. Today you can find logic synthesis tools being offered by the big three in EDA: Synopsys, Cadence, Mentor Graphics. Since RTL synthesis has been around for decades you may be lulled into thinking that all approaches are about the same, and that the market is mature and kind of static. If that was really true, then why did Synopsys have to recently re-write their tool from scratch in order to meet the challenges of capacity, speed and Quality Of Results (QOR)?
Mentor Graphics acquired Oasys Design Systemsabout 13 months ago, and with that move filled a gap in their digital implementation tool flow by adding RTL synthesis. Engineers at Mentor authored an 8 page white paper to explain their approach and how it’s different than anything else out there. In general a modern synthesis tool must provide SoC designers with:
- High capacity, 100 million+ gates or cells
- Fast runtimes in hours, not days or weeks
- Acceptable QoR
- Physical awareness to decrease design closure times
- Standard inputs: Verilog, SystemVerilog, VHDL
Related – Oasys Bakes a PIE
A traditional logic synthesis approach translates RTL code into gates, then optimizes the gates to meet your design specifications. More modern approaches start to take physical information like estimated routing capacitances back into the optimization phase. Optimizing the design at the gate level is a low-level approach, is very localized, and can require long run times as the design size increases.
This approach can force users to break their design up into smaller pieces and have separate synthesis runs, which in turn will increase design closure times.
Without using a full-chip floorplan, a traditional synthesis tool will cause many iterations between front-end and back-end designers trying to reach design closure. You don’t even know where the congestion bottlenecks are with this approach.
Back in 2004 when Oasys was founded, they knew that there had to be a better way to approach RTL synthesis, and so the RealTime Designer product came to life starting in 2009, then acquired by Mentor in December 2013. Along the way Oasys received funding from Intel Capital and Xilinx, certainly two very large customers with some of the highest complexity SoC devices. Here’s what makes the new approach different:
- Includes full chip-level physical synthesis
- Optimization at RTL level
- Identifies and resolves timing, routability and power issues earlier in the design cycle
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An immediate benefit of this approach is that you can run RTL synthesis on a design with 10’s of millions of gates in just a few hours, not days. With physical synthesis the tool partitions the RTL into partitions that are placed, then using physical library cells and accurately estimating interconnect between cells. Both placement and timing information gets updated with every optimization transformation. Even congestion maps give early feedback to an RTL designer about routing issues that may limit the physical implementation.
Routing Congestion Map
The RealTime Designer tool will automatically create a floorplan based upon each high-level module and other design data. Modules from the RTL are then assigned to physical regions of the floorplan. All of this physical placement info creates accurate interconnect estimates. You can add in any custom blocks or other hard macros required for your design, along with RTL source code. Here’s a picture of the floorplanning, placement an optimization steps:
Related – Oasys Announces Floorplan Compiler
Because RealTime Designer produces results so quickly, you can now afford to do some explorations to trade off power, performance, area, congestion and DFT goals.
Instead of separating logical and physical design, with this approach you can actually begin to cross-probe between RTL source code and critical paths in the physical design after floorplanning:
Cross-probing between design views
Within RealTime Designer you’ll find both static and dynamic power analysis, plus support for:
- Multiple Vt libraries
- Advanced clock gating
- Multi-Corner Multi-Mode (MCMM)
- Power density driven placement
- UPF and multi-VDD
- Interactive and batch analysis
DFT engineers can use the scan insertion feature, which minimizes interconnect in the scan chains and creates a standard scandef file for Place and Route or ATPG tools:
Left: design without scan chain ordering.
Right: design with scan chains ordered with physical placement.
Engineers at Oasys, now Mentor Graphics, have developed a new approach to RTL synthesis that can handle 100M+ gate capacity, and produce results up to 10X faster than older architectures, while meeting your PPA (Power, Performance, Area) specifications. Read the complete 8 page White Paper here for more details.