Cross-viewing improves ASIC & FPGA debug efficiency

Cross-viewing improves ASIC & FPGA debug efficiency
by Don Dingee on 04-20-2016 at 4:00 pm

We introduced the philosophy behind the Blue Pearl Software suite of tools for front-end analysis of ASIC & FPGA designs in a recent post. As we said in that discussion, effective automation helps find and remedy issues as each re-synthesis potentially turns up new defects. Why do Blue Pearl users say their tool suite is easier… Read More


Not All RTL Synthesis Approaches are the Same

Not All RTL Synthesis Approaches are the Same
by Daniel Payne on 01-20-2015 at 7:00 pm

My first experience with logic synthesis was at Silicon Compilers in the late 1980s using a tool called Genesil. Process technology since that time has moved from 3 um down to 20 nm, so there are new challenges for RTL synthesis. Today you can find logic synthesis tools being offered by the big three in EDA: Synopsys, Cadence, MentorRead More


Synthesizing rad-tolerant RTL for FPGAs

Synthesizing rad-tolerant RTL for FPGAs
by Don Dingee on 12-09-2014 at 4:00 pm

The maiden voyage of NASA’s Orion spacecraft brought a raft of articles about how the flight computer inside is “no smarter than your phone,” running on wheezing IBM PowerPC 750FX processors. NASA’s deputy manager for Orion avionics, Matt Lemke, admits the configuration is already obsolete – at least in commercial terms. … Read More


Floorplanning Merged With Synthesis

Floorplanning Merged With Synthesis
by Paul McLellan on 10-02-2013 at 2:45 pm

One area of iteration that is becoming more problematic is between floorplanning and synthesis. So much of timing is driven by placement that fixing timing and even power often involves not just re-synthesis and re-placement but alterations to the floorplan. The Achilles heel of existing methods is that floorplanning tools … Read More