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EDA

Electronic Design Automation

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How ARM Implemented a Mali GPU using Logic Synthesis and Place/Route Tools

How ARM Implemented a Mali GPU using Logic Synthesis and Place/Route Tools
by Daniel Payne on 07-17-2015 at 12:00 pm
Categories: EDA, Synopsys

ARM is a well-known semiconductor IP provider and they often create a reference design so that SoC companies can have a starting point to work with. On the GPU side of IP the ARM engineers have an architecture called Mali, and a recent webinar hosted by Synopsys reviewed how the physical design area was minimized by using a combination… Read More

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How PowerArtist Interfaces with Emulators

How PowerArtist Interfaces with Emulators
by Pawan Fangaria on 07-16-2015 at 5:00 pm
Categories: Ansys, Inc., EDA, Siemens EDA

Last month in DAC I could see some of the top innovations in the EDA world. EDA is a key enabler for advances in semiconductor designs. Among a number of innovations worth mentioning (about which I blogged just after DAC), the integration of Mentor’s Veloce with ANSYS’ PowerArtist for power analysis of live applications caught my… Read More

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Coventor SEMulator3D, Now With Added Dopant, Diffusion, Illumination and More

Coventor SEMulator3D, Now With Added Dopant, Diffusion, Illumination and More
by Paul McLellan on 07-16-2015 at 7:00 am
Categories: Coventor, EDA

Coventor just rolled out the latest version of SEMulator3D, their virtual fabrication tool. Very conveniently it is SEMICON West this week and they have a booth. I dropped by and got a demo from David Fried, Coventor’s CTO about all the new stuff. He’s very proud of SEMulator3D’s new logo but mostly he is proud… Read More

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How Emulation Enables Complex Power Intent Modeling

How Emulation Enables Complex Power Intent Modeling
by Pawan Fangaria on 07-15-2015 at 12:00 pm
Categories: Cadence, EDA

As the number of CPU, GPU, and IP is growing in an SoC, power management is becoming more and more a complex task in itself. A single tool or methodology may not be enough for complete power management and verification of an SoC. In an SoC, there can be multiple modes of operations involving hardware and software interactions, different… Read More

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Benefits of RTL Power Budgeting

Benefits of RTL Power Budgeting
by Daniel Payne on 07-15-2015 at 4:00 am
Categories: Ansys, Inc., EDA

Only one company at the recent DAC conference and exhibit had a set of four interacting disciplines: Fluids, Structures, Electronics and Systems. Did you guess that the company was ANSYS? I get so IC focused at times that I almost forget that chips plug into boards, that boards become systems, and that systems drive and control mechanical… Read More

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Improve RTL Physically for Design Quality & Convergence

Improve RTL Physically for Design Quality & Convergence
by Pawan Fangaria on 07-13-2015 at 12:00 pm
Categories: EDA

The SoC design teams are usually divided between front-end and back-end specialties. It is neither practical nor advisable to combine the two teams in order to better tackle the back-end issues upfront during the front-end design. However, a common problem is that the issues at the layout stage have very little scope for resolution… Read More

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Conquering the Next IoT Challenges with FPGA-Based Prototyping

Conquering the Next IoT Challenges with FPGA-Based Prototyping
by Daniel Nenni on 07-12-2015 at 12:00 pm
Categories: EDA, FPGA, S2C EDA, Xilinx

The need for ever-connected devices is skyrocketing. As I fiddle with my myriad of electronic devices that seem to power my life, I usually end up wishing that all of them could be interconnected and controlled through the Internet. The truth is, only a handful of my devices are able to fulfill that wish, but the need is there and developers… Read More

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Which High B/W Memory to Select after DDR4?

Which High B/W Memory to Select after DDR4?
by Eric Esteve on 07-11-2015 at 6:00 am
Categories: Cadence, IP

Once upon a time, RAM technology was the driver of the semiconductor process. DRAM products were the first to be designed on a newest technology node and DRAM was used as a process driver. It was 30 years ago and the most aggressive process nodes were ranging between 1um and 1.5 um (1 500 nm!). Then in the 1990 the Synchronous Dynamic … Read More

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Tackling Layout Gradient Effects in 16 nm FinFET using Layout Automation

Tackling Layout Gradient Effects in 16 nm FinFET using Layout Automation
by Daniel Payne on 07-10-2015 at 12:00 pm
Categories: Cadence, EDA, FinFET

My first exposure to automating IC layout was back in the 1980’s at Intel where I coded a layout compiler to auto-generate about 6% of a graphics processor chip. The need to use automation for IC layout continues today, and with the advent of FinFET technology there are some new challenges like layout gradient effects that … Read More

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Updates for Effective Collaboration

Updates for Effective Collaboration
by Paul McLellan on 07-09-2015 at 7:00 am
Categories: EDA, Perforce

Managing any design data management system requires a policy on how often users should be submitting their changes to the central repository. If users commit frequently with less local testing then other users will more likely see errors. If commits are done less often, but with better testing, then other users are protected from… Read More