100X800 Banner (1)
WP_Term Object
(
    [term_id] => 157
    [name] => EDA
    [slug] => eda
    [term_group] => 0
    [term_taxonomy_id] => 157
    [taxonomy] => category
    [description] => Electronic Design Automation
    [parent] => 0
    [count] => 4363
    [filter] => raw
    [cat_ID] => 157
    [category_count] => 4363
    [category_description] => Electronic Design Automation
    [cat_name] => EDA
    [category_nicename] => eda
    [category_parent] => 0
    [is_post] => 
)
EDA

Electronic Design Automation

Posted on

Cadence is again the best EDA company to work for!

Cadence is again the best EDA company to work for!
by Daniel Nenni on 03-10-2016 at 7:00 am
Categories: Cadence, EDA

We wrote about the history of Cadence in preparation for our book “Fabless: The Transformation of the Semiconductor Industry” in 2012. EDA played a key role in enabling the fabless semiconductor revolution and Cadence was right there at the beginning. Famed EETimes editor Richard Goering helped us with the book and the Cadence… Read More

Posted on

How China can Lead in the Semiconductor Industry

How China can Lead in the Semiconductor Industry
by Pawan Fangaria on 03-06-2016 at 8:00 pm
Categories: EDA, Foundries

Since a few years China has been very aggressive in acquiring semiconductor companies around the world. Last year, Chinese government along with PE (Private Equity) and other investors in China announced an ambitious plan under which more than $150 billion were to be invested over next 5 to 10 years in developing semiconductor… Read More

Posted on

Ajoy – History, Perspectives and Crossing the Chasm

Ajoy – History, Perspectives and Crossing the Chasm
by Bernard Murphy on 03-06-2016 at 4:00 pm
Categories: EDA, Synopsys

EDAC hosted an event at DVCon this week where Jim Hogan interviewed Ajoy Bose (CEO of Atrenta prior to its acquisition by Synopsys). The nominal purpose was to talk about turning a venture into a valuable enterprise. This was covered but, in Jim’s way, it was really a more wide-ranging and personal interview. This is an abstract of… Read More

Posted on

IC Design and OpenAccess

IC Design and OpenAccess
by Daniel Payne on 03-06-2016 at 12:00 pm
Categories: EDA

EDA vendors have long used proprietary file and database formats to keep their users locked into their specific tool flow and keep any competitors from sharing in the IC design process. Along the way the actual users of EDA tools have often requested and helped to create interoperable flows so that they could mix and match multiple… Read More

Posted on

Dr. Walden Rhines on the Past Present and Future!

Dr. Walden Rhines on the Past Present and Future!
by Daniel Nenni on 03-06-2016 at 7:00 am
Categories: EDA, Siemens EDA

Who can present seventy six slides in sixty minutes, still have time for questions, AND make it interesting? Dr. Walden Rhines that’s who. Here is a link to the presentation but I have to warn you, it is a 100MB PDF file:

Design Verification Challenges: Past, Present, and Future

The DVCon conference was well attended again this year… Read More

Posted on

A Brief History of Defacto Technologies

A Brief History of Defacto Technologies
by Pawan Fangaria on 03-04-2016 at 7:00 am
Categories: Defacto Technologies, EDA

In early 2000s, semiconductor design at RTL level was gaining momentum. The idea was to process more design steps such as insertion of test and other design structures upfront at the RTL level. The design optimization and verification were to be done at the RTL level to reduce long iterations through gate level design because changes… Read More

Posted on

Solving the Next Big SoC Challenges with FPGA Prototyping

Solving the Next Big SoC Challenges with FPGA Prototyping
by Daniel Nenni on 03-01-2016 at 4:00 pm
Categories: EDA, FPGA, S2C EDA

The health of the semiconductor industry revolves around the “start”. Chip design starts translate to wafer starts, and both support customer design wins and product shipments. Roadmaps develop for expanding product offerings, and capital expenditures flow in to add capacity enabling more chip designs and wafer starts. If… Read More

Posted on

Multi-Level Debugging Made Easy for SoC Development

Multi-Level Debugging Made Easy for SoC Development
by Pawan Fangaria on 03-01-2016 at 7:00 am
Categories: Concept Engineering, EDA

An SoC can have a collection of multiple blocks and IPs from different sources integrated together along with several other analog and digital components within a native environment. The IPs can be at different levels of abstractions; their RTL descriptions can be in different languages such as Verilog, VHDL, or SystemVerilog.… Read More

Posted on

FPGA tools for more predictive needs in critical

FPGA tools for more predictive needs in critical
by Don Dingee on 02-29-2016 at 4:00 pm
Categories: Blue Pearl Software, EDA, FPGA

“Find bugs earlier.” Every software developer has heard that mantra. In many ways, SoC and FPGA design has become very similar to software development – but in a few crucial ways, it is very different. Those differences raise a new question we should be asking about uncovering defects: earlier than when?… Read More