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How has 20nm Changed the Semiconductor Ecosystem?

How has 20nm Changed the Semiconductor Ecosystem?
by Daniel Nenni on 07-15-2012 at 7:30 pm


What does mango beer have to do with semiconductor design and manufacturing? At a table of beer drinkers from around the world I would have never thought fruity beer would pass a taste test, not even close. As it turns out, the mango beer is very good! Same goes for 20nm planar devices. “Will not work”, “Will not yield”, “Will not scale”,… Read More


Cadence at Semicon West Next Week: 2.5D and 3D

Cadence at Semicon West Next Week: 2.5D and 3D
by Paul McLellan on 07-05-2012 at 5:32 pm

Next week it is Semicon West in the Moscone Center from Tuesday to Thursday, July 10-12th. Cadence will be on a panel session during a session entitled The 2.5D and 3D packaging landscape for 2015 and beyond. This starts with 3 short keynotes:

  • 1.10pm to 1.25pm: Dr John Xie of Altera on Interposer integration through chip on wafer on
Read More

Cadence/TSMC 3D

Cadence/TSMC 3D
by Paul McLellan on 06-11-2012 at 5:16 pm

Mark Twain remarked that everyone talks about the weather but nobody does anything about it. 3D ICs seems to be a bit like that. Over the last couple of years there have been lots of people talking about 3D but very little that has actually been manufactured. In addition to the weather, everyone talks about Xilinx’s 3D Virtex… Read More


Collaboration at 28nm, 20nm and 14nm

Collaboration at 28nm, 20nm and 14nm
by Daniel Payne on 06-06-2012 at 11:23 am


Wednesday morning I attended a panel discussion with: ARM, IBM, Cadence, GLOBALFOUNDRIES and Samsung.

The panelists all sang the same song of collaboration between EDA, IP and Foundry to enable 28nm, 20nm and even 14nm.… Read More


CDN Live in Munich: Cadence is back on track!

CDN Live in Munich: Cadence is back on track!
by Eric Esteve on 05-18-2012 at 3:44 am

Before going to Munich to attend to CDN-Live, I took a look at the agenda to figure out which presentations to attend, and I must say it was not so easy to choose: CDN Live agendais dense, with multiple tracks running in parallel (Custom Design, Digital Implementations, Design IP, Functional Verifications and Verification IP, PCB… Read More


Semiconductor Ecosystem Keynotes: ARM 2012

Semiconductor Ecosystem Keynotes: ARM 2012
by Daniel Nenni on 05-17-2012 at 5:00 pm

Yesterday’s SEMICO IP Ecosystem Conference was well worth the time. Everybody was there: ARM, Synopsys, Cadence, Mentor Graphics, GlobalFoundries, TSMC, MIPS, Tensilica, AMD, Atrenta, Sonics, and Tabula, everybody except Intel of course. What do Intel and I have in common? We don’t play well with others…

First up was… Read More


Cadence Update 2012!

Cadence Update 2012!
by Daniel Nenni on 05-14-2012 at 9:00 pm

What’s new at Cadence? Quite a bit actually. I have always been a Cadence fan, I mean really, they gave birth to modern EDA. Unfortunately, Cadence really lost me during the Avant! legal action, the Mike Fister years, and EDA360. Recently, however, Cadence has made some big changes that will definitely get them back on my good side.… Read More


28nm Layout Needs Signoff Quality at Design Time

28nm Layout Needs Signoff Quality at Design Time
by Pawan Fangaria on 05-03-2012 at 8:30 pm

We are all aware that at 28nm and below several types of complex layout effects manifest themselves into the design and pose a herculean task, with several re-spins to correct them at pre-tapeout. It’s apparent that the layout needs to be correct by construction at the very beginning during the design stage.

Having worked at CadenceRead More