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Cadence
Posted on

20nm IC production needs more than a ready Foundry

20nm IC production needs more than a ready Foundry
by Pawan Fangaria on 08-23-2013 at 11:00 am
Categories: Arm, Cadence, EDA, TSMC

I think by now all of us know, or have heard about 20nm process node, its PPA (Power, Performance, Area) advantages and challenges (complexity of high design size and density, heterogeneity, variability, stress, lithography complexities, LDEs and so on). I’m not going to get into the details of these challenges, but will ponder… Read More

Posted on

Happy Birthday Dear Cadence…

Happy Birthday Dear Cadence…
by Paul McLellan on 08-14-2013 at 8:30 pm
Categories: Cadence, EDA

Cadence is 25 years old this year, on June 1st if you want to be precise.

The most direct ancestor of Cadence was SDA (which might or might not have stood for Solomon Design Automation). SDA was founded by Jim Solomon in 1983. It turns out that a guy I shared an office with while we were both doing our PhDs in Edinburgh Scotland was one of … Read More

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Data Centers accounts for 2 to 3% of WW Energy Consumption!

Data Centers accounts for 2 to 3% of WW Energy Consumption!
by Eric Esteve on 07-11-2013 at 8:19 am
Categories: Cadence, EDA

Do you think this figure will go down? Considering the massive move to Mobile equipment, pushing to de-localize your storage medium to instead use the cloud capabilities, and looking at the huge number of people buying smartphone and tablet in emerging countries, no doubt that Data Center related energy consumption is expected… Read More

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Swap and Play Extended To Chip Fabric and Memory Controllers

Swap and Play Extended To Chip Fabric and Memory Controllers
by Paul McLellan on 06-16-2013 at 9:08 am
Categories: Arteris, Cadence, EDA, IP

Virtual platforms enable software development to take place on a model of an electronic system. What everyone would like is models that are fast and accurate but that is simply not possible. Fast models are fast because they don’t model everything at the signal level. And accurate models get to be accurate by handling a lot of detail… Read More

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Hardware Assisted Verification

Hardware Assisted Verification
by Paul McLellan on 06-10-2013 at 9:00 pm
Categories: Cadence, EDA, Events, Siemens EDA, Synopsys

On the Tuesday of DAC I moderated a panel session on Hardware Assisted Verification in 10 Years: More Need, More Speed. Although this topic obviously could include FPGA-based prototyping, in fact we spent pretty much the whole time talking about emulation. Gary Smith, on Sunday night, actually set up things by pointing out that… Read More

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Custom Physical IC Design update from Cadence

Custom Physical IC Design update from Cadence
by Daniel Payne on 06-10-2013 at 8:05 pm
Categories: Cadence, EDA

Custom IC design and layout is becoming more difficult at 20nm and smaller nodes, so the EDA tools have to get smarter and work harder for us in order to maintain productivity with the fewest iterations to reach our specs. Dave Stylesand John Stabenow of Cadence met with me last Monday in Austin at the DAC exhibit area.


John Stabenow… Read More

Posted on

DAC: Tempus Lunch

DAC: Tempus Lunch
by Paul McLellan on 06-06-2013 at 4:03 pm
Categories: Cadence, EDA

I had time for lunch on Monday. That is to say, there was a Cadence panel session about Has Timing Signoff Innovation has become and Oxymoron? What Happened and How Do We Fix It?

The moderator was Brian Fuller, lately of EE Times but now Editor-in-Chief at Cadence (I’m not sure quite what it means either). On the panel were Dipesh… Read More

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The Only DM Platform Integrated with All Major Analog and Custom IC Design Flows

The Only DM Platform Integrated with All Major Analog and Custom IC Design Flows
by Daniel Nenni on 05-22-2013 at 10:00 am
Categories: Cadence, Cliosoft, EDA

As I have mentioned before, Cliosoft is the biggest little company in EDA with the most talked about products on SemiWiki. At DAC, ClioSoft will introduce integrated SOS design management (DM) solutions providing revision control, design management and multi-site team collaboration for Aglient Technologies’ Advanced Design… Read More

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Transistor-Level Update from Cadence at DAC

Transistor-Level Update from Cadence at DAC
by Daniel Payne on 05-20-2013 at 7:47 pm
Categories: Cadence, EDA

My 8 years as an IC circuit designer were at the transistor-level, so if that interests you as well then consider what there is to see from Cadence at DAC this year. IC design technology is changing quickly, so keeping up to date is important for your job security and continual education goals.

Here’s what I would recommend attending… Read More