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WIKI Multi FPGA Design Partitioning 800x100 
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Aldec
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Conflating ISO 26262 and DO-254

Conflating ISO 26262 and DO-254
by Bernard Murphy on 01-30-2018 at 7:00 am
Categories: Aldec, Automotive, EDA, FPGA

If you’re in the ASIC business, by now you should have a rough understanding of ISO 26262, the safety standard for automotive electronics. You may be less familiar with DO-254 which has somewhat similar intent for airborne electronics. Unless, that is, you design with FPGAs in which case your familiarity may be the other way around… Read More

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Webinar: ISO 26262 and DO-254: Achieving Compliance to Both

Webinar: ISO 26262 and DO-254: Achieving Compliance to Both
by Bernard Murphy on 01-11-2018 at 7:00 am
Categories: Aldec, Automotive, EDA, FPGA

It’s near-impossible to read anything today about electronic design for cars without running into the ISO 26262 standard. If you design airborne electronic hardware, you’re likely very familiar with the DO-254 standard. But what do you do if you want to design a product to serve both markets? It looks like aircraft makers are increasingly… Read More

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Aldec and High-Performance Computing

Aldec and High-Performance Computing
by Bernard Murphy on 12-21-2017 at 7:00 am
Categories: Aldec, EDA, Events, FPGA

Aldec continues to claim a bigger seat at the table, most recently in their attendance at SC17, the supercomputing conference hosted last month in Denver. I’m really not sure how to categorize Aldec now. EDA company seems to miss the mark by a wide margin. Prototyping company? Perhaps, though they have a much stronger focus on end-applications… Read More

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The DIY Syndrome

The DIY Syndrome
by Bernard Murphy on 11-09-2017 at 7:00 am
Categories: Aldec, EDA

When facing a new design objective, we check off all the established tools and flows we know we are going to need. For everything else, we default to an expectation that we will paper over the gaps with scripting, documentation and spreadsheets. And why not? When we don’t know what we will have to deal with, in documentation, scheduling,… Read More

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An IIot Gateway to the Cloud

An IIot Gateway to the Cloud
by Bernard Murphy on 10-10-2017 at 7:00 am
Categories: Aldec, EDA, FPGA, IoT, Security

A piece of learning we all seem to have gained from practical considerations of IoT infrastructure is that no, it doesn’t make sense to ship all the data from an IoT edge device to the cloud and let the cloud do all the computational heavy lifting. On the face of it that idea seemed good – all those edge devices could be super cheap (silicon… Read More

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Partitioning for Prototypes

Partitioning for Prototypes
by Bernard Murphy on 09-19-2017 at 7:00 am
Categories: Aldec, EDA, FPGA, Prototyping

I earlier wrote a piece to make you aware of a webinar to be hosted by Aldec on some of their capabilities for partitioning large designs for prototyping. That webinar has now been broadcast and I have provided a link to the recorded version at the end of this piece. The webinar gets into the details of how exactly you would use the software… Read More

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Webinar: Aiding ASIC Design Partitioning for multi-FPGA Prototyping

Webinar: Aiding ASIC Design Partitioning for multi-FPGA Prototyping
by Bernard Murphy on 09-07-2017 at 4:00 pm
Categories: Aldec, EDA, FPGA, Prototyping

The advantages of prototyping a hardware design on a FPGA platform are widely recognized, for software development, debug and regression in particular while the ultimate ASIC hardware is still in development. And if your design will fit into a single FPGA, this is not an especially challenging task (as long as you know your way … Read More

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Webinar: Fast-Track to Riviera-PRO

Webinar: Fast-Track to Riviera-PRO
by Bernard Murphy on 08-11-2017 at 7:00 am
Categories: Aldec, EDA, FPGA

Whether you’re right out of college, starting on your first design, a burn-and-churn designer thinking there must be a better way or an ASIC designer wanting to do a little prototyping, this webinar may be for you. It’s a fast start on using the Aldec Riviera-PRO platform for verification setup, run and debug, and more. There are … Read More

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Cloud-Based Emulation

Cloud-Based Emulation
by Bernard Murphy on 08-02-2017 at 7:00 am
Categories: Aldec, EDA, FPGA
12 Comments

At the risk of attracting contempt from terminology purists, I think most of us would agree that emulation is a great way to prototype a hardware design before you commit to building, especially when you need to test system software together with that prototype. But setting up your own emulation resource isn’t for everyone. The … Read More

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HW and SW Co-verification for Xilinx Zynq SoC FPGAs

HW and SW Co-verification for Xilinx Zynq SoC FPGAs
by Daniel Payne on 07-03-2017 at 12:00 pm
Categories: Aldec, EDA, FPGA

It constantly amazes me at how much FGPA companies like Xilinx have done to bring ARM-based CPUs into a programmable SoC along with FPGA glue logic. Xilinx offers the Zynq 7000 and Zynq UltraScale+ SoCs to systems designers as a way to quickly get their ideas into the marketplace. A side effect of all this programability and flexibility… Read More