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SOC Design Techniques that Enable Autonomous Vehicles

SOC Design Techniques that Enable Autonomous Vehicles
by Tom Simon on 10-11-2016 at 4:00 pm

Robots – we have all been waiting for them since we were young. We watched Star Wars, or in the case of the slightly longer-lived of us, we watched Forbidden Planet or Lost in Space. We knew that our future robot friends would be able to move around and interact with their environment. What we did not foresee long ago was that instead of… Read More


Next Book Signing: Linley Processor Conference 2016!

Next Book Signing: Linley Processor Conference 2016!
by Daniel Nenni on 09-20-2016 at 12:00 pm

It is a busy month for book signings but it is a pleasure to do it for the greater good of the semiconductor industry. It really is an honor to meet the people who keep our electronic devices on the leading edge of technology, absolutely.

The Linley Processor Conference is on September 27[SUP]th[/SUP]and 28[SUP]th[/SUP] at the Hyatt… Read More


How to Bring Coherency to the World of Cache Memory

How to Bring Coherency to the World of Cache Memory
by Tom Simon on 07-11-2016 at 12:00 pm

As the size and complexity of System On Chip design has rapidly expanded in recent years, the need to use cache memory to improve throughput and reduce power has increased as well. Originally, cache memory was used to prevent what was then a single processor from making expensive off chip access for program or data memory. With the… Read More


Arteris Unveils Solution for Heterogeneous Cache Coherent SOC’s

Arteris Unveils Solution for Heterogeneous Cache Coherent SOC’s
by Tom Simon on 05-30-2016 at 12:00 pm

Designing SOC’s for markets like automotive and mobile electronics requires taking advantage of every opportunity for optimization. One way to do this is through building a cache coherent system to boost speed and reduce power. Recently, NXP decided to go about this on their automotive MCU based SOC’s by using Arteris’ just-announced… Read More


Cache Coherent Systems Get a Boost from New Technology

Cache Coherent Systems Get a Boost from New Technology
by Tom Simon on 05-20-2016 at 12:00 pm

The speed and power penalties for accessing system RAM affect everything from artificial intelligence platforms to IoT sensor nodes. There is a huge power and performance overhead when the various IP blocks in an SOC need to go to DRAM. Memory caches have become essential to SOC design to reduce these adverse effects. However, … Read More


Enterprise SSD SOC’s Call for a Different Interconnect Approach

Enterprise SSD SOC’s Call for a Different Interconnect Approach
by Tom Simon on 03-01-2016 at 12:00 pm

The move to SSD storage for enterprise use brings with it the need for difficult to design enterprise capable SSD controller SOC’s. The benefits of SSD in hyperscale data centers are clear. SSD’s offer higher reliability due to the elimination of moving parts. They have a smaller foot print, use less power and offer much better performance.… Read More


Smart TV Chipset: 4 Key Takeaways from Interconnect IP

Smart TV Chipset: 4 Key Takeaways from Interconnect IP
by Majeed Ahmad on 01-26-2016 at 4:00 pm

The ultra high-definition (UHD) or 4K TV hardware is leading to insanely powerful chipsets in the age of Netflix, and that is taking the system-on-chip (SoC) design to a whole new level of complexity. Take the case of Samsung’s new chipset for SUHD TVs that boasts more than 100 IP interfaces.

Here, apart from the usual suspects… Read More


How Wireless Modem IP is Aiding Roadmap to 5G Chipsets

How Wireless Modem IP is Aiding Roadmap to 5G Chipsets
by Majeed Ahmad on 12-22-2015 at 4:00 pm

The semiconductor industry is steadily charting its course toward 5G chipsets with the availability of extremely complex system-on-chip (SoC) designs that support the surge of data traffic over next-generation wireless networks. Take Blu Wireless Technology, for instance, the IP supplier from Britain that is using the Arteris… Read More


Interconnect Watch: 3 Chip Design Merits for Network Applications

Interconnect Watch: 3 Chip Design Merits for Network Applications
by Majeed Ahmad on 10-21-2015 at 4:00 pm

The countdown to the end of Moore’s Law is coinciding with the rising complexity in system-on-chip (SoC) designs. And that’s not a mere coincidence. The leverage that has long been coming from shrinking process nodes in terms of cost, performance and power benefits is now increasingly being accomplished through… Read More


Optimizing Quality-of-Service in a Network-on-Chip Architecture

Optimizing Quality-of-Service in a Network-on-Chip Architecture
by Tom Dillinger on 10-13-2015 at 12:00 pm

The Linley Group is well-known for their esteemed Microprocessor Report publication, now in its 28th year. Accompanying their repertoire of industry reports, TLG also sponsors regular conferences, highlighting the latest developments in processor architecture and implementation.

One of the highlights of the conference… Read More